Verilog(redirected from .v)
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VerilogAn HDL (hardware description language) used to design electronic systems at the component, board and system level. Developed by Phil Morby at Gateway Design Automation, it was introduced in 1985 along with Verilog-XL, a logic simulator.
By the late 1980s, Verilog was the de facto standard for proprietary HDLs. After Cadence Design Automation acquired it in 1989 and put it into the public domain in 1990, it became the IEEE 1364 standard in 1995 (Verilog 95).
SystemVerilog is an enhanced version of Verilog developed by Accellera (www.accellera.org), an industry organization formed in 2000 by the consolidation of Open Verilog International (OVI) and VHDL International. Verilog and VHDL are the two major HDLs. See VHDL and RTL.
|Verilog and VHDL are the most popular HDLs. These examples show a circuit described in RTL in both languages and the resulting schematic of the gate level netlist created after synthesis (below). (Language and schematic examples from "HDL Chip Design" courtesy of Douglas J. Smith.)|