6T SRAM


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6T SRAM

(6 Transistor SRAM) See static RAM.
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UMC's URAM effectively addresses the needs of SoC designs for a broad range of applications, including storage media, communications, and graphics and imaging systems, by providing a high-density memory that delivers up to a 50 percent area reduction over standard 6T SRAM.
URAM's ultra high density, 1/4 to 1/5 the size of 6T SRAM with a macro area of approximately 1/2 to 1/3 times the size of SRAM, allows for smaller overall form factor so that designers can fit more functions within a smaller chip area.
The capacitor is integrated vertically into the cell structure, so there is no increase in cell size, and the cell also contains polysilicon thin film transistors (TFTs) to enable the small 6T SRAM cell.
When configured for sub 5ns speed, McRAM achieves a cell size much smaller than that of typical 6T SRAM implementation.
The DRAM structure also results in a memory cell that is only one-tenth the size of a 6T SRAM cell using the same lithography node.
The 4Mb SRAM devices feature a 65-nanometer gate length and the world's smallest 6T SRAM cell, measuring less than 1.
Now the second-generation 1T-SRAM-M technology challenges even the data-retaining standby power capabilities of 6T SRAM, with standby current capabilities of just 10 micro amps per megabit or less when implemented in TSMC 0.
Fu-Chieh Hsu, MoSys CEO, stated, "Over the last 2 years, MoSys has consistently demonstrated the many fundamental advantages of our patented, embedded 1T-SRAM(R) technology over traditional 6T SRAM and embedded DRAM.
Traditional 6T SRAM suffers from the fundamental CMOS scaling limit of sub-threshold voltage, which must be a small fraction of the supply voltage.
13-micron silicon was a 6T SRAM developed in November of 1999.