Address Strobe


Also found in: Acronyms.

Address Strobe

(storage)
(AS) One of the input signals of a memory device, especially semiconductor memory, which is asserted to tell the memory device that the address inputs are valid. Upon receiving this signal the selected memory device starts the memory access (read/write) indicated by its other inputs.

It may be driven directly by the processor or by a memory controller.
References in periodicals archive ?
The new 256-Mb and 128-Mb devices are targeted for the most stringent "2-2-2" goal for CL2 (Column Address Strobe Latency 2) performance, as described in Intel's PC SDRAM specification.
The new Samsung devices also meet the specifications supporting Column Address Strobe (CAS) Latency 2 and 3 for high performance applications.
With EDO, output data remains valid even when the column address strobe (CAS) goes HIGH.

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