asynchronous logic

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asynchronous logic

[ā′siŋ·krə·nəs ′läj·ik]
(electronics)
A logic network in which the speed of operation depends only on the signal propagation through the network.

asynchronous logic

(architecture)
A data-driven circuit design technique where, instead of the components sharing a common clock and exchanging data on clock edges, data is passed on as soon as it is available. This removes the need to distribute a common clock signal throughout the circuit with acceptable clock skew. It also helps to reduce power dissipation in CMOS circuits because gates only switch when they are doing useful work rather than on every clock edge.

There are many kinds of asynchronous logic. Data signals may use either "dual rail encoding" or "data bundling". Each dual rail encoded Boolean is implemented as two wires. This allows the value and the timing information to be communicated for each data bit. Bundled data has one wire for each data bit and another for timing. Level sensitive circuits typically represent a logic one by a high voltage and a logic zero by a low voltage whereas transition signalling uses a change in the signal level to convey information. A speed independent design is tolerant to variations in gate speeds but not to propagation delays in wires; a delay insensitive circuit is tolerant to variations in wire delays as well.

The purest form of circuit is delay-insensitive and uses dual-rail encoding with transition signalling. A transition on one wire indicates the arrival of a zero, a transition on the other the arrival of a one. The levels on the wires are of no significance. Such an approach enables the design of fully delay-insensitive circuits and automatic layout as the delays introduced by the layout compiler can't affect the functionality (only the performance). Level sensitive designs can use simpler, stateless logic gates but require a "return to zero" phase in each transition.

http://cs.man.ac.uk/amulet/async/.
References in periodicals archive ?
Added to this edition are materials on CMOS logic; modern two-level and multi-level logic synthesis methods; logic design for emerging nanotechnologies; test generation, design for testability, and built-in self-test for combinational and sequential circuits; and modern asynchronous circuit synthesis techniques, among other recent topics.
The company has begun marketing the technology, an asynchronous circuit architecture called Sleep Convention Logic[TM] (SCL), which it sees as the breakthrough of the decade in integrated circuit design.
Using Tiempo innovative design flow, such highly performing hardware can be described with a standard hardware description language, synthesized with ACC, Tiempo unique asynchronous circuit compiler, then verified and placed-and-routed with standard simulation and back-end tools.
Tiempo licenses Verific's SystemVerilog analyzer and static elaborator to serve as the front end to its Asynchronous Circuit Compiler (ACC), synthesis software that generates asynchronous and delay-insensitive circuits from a model written in SystemVerilog.
Fulcrum Microsystems, a pioneer in asynchronous circuit design (clockless chips), is a fabless semiconductor company that is leveraging its patented Delay-Insensitive design methodology to develop clockless system-on-chip (SOC) solutions that offer significant advantages in power, performance and time to market over those designed using traditional synchronous VLSI design methods.
The themes are model transformations, concurrent system verification, conformance and run-time techniques, stochastic systems, asynchronous circuits, synchronous and heterogeneous systems, and timed systems.
International Symposium on Asynchronous Circuits and Systems (16th: 2010: Grenoble, France)
Beerel and Julio Arceo, "High-Performance Asynchronous Pipeline Circuits," Proceedings of International symposium on Advance Research in Asynchronous circuits and systems, October, 1996.
Using Questa CDC's static analysis capabilities, iD's design teams can quickly and easily uncover bugs in asynchronous circuits and avoid discovering them late in the design cycle or during lab verification.
The product handles combinational and sequential logic, synchronous and asynchronous circuits, ASICs and full-custom ICs, and low- and high-complexity chips including those with embedded functions such as RAM.
The 15 papers selected for the April 2008 symposium present recent research on data-driven asynchronous circuits, variability and power, latch protocols and pipelines, efficient and reliable schemes for computation and communication, and verification of asynchronous controllers.
Other coverage is of SoCs and asynchronous circuits, aging and wearout issues and mitigation approaches, radiation effects, signal integrity and error compensation, SER trends, fault tolerance, on-line and processor- based testing, and self-checking and self-testing.
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