Printer Friendly
Dictionary, Encyclopedia and Thesaurus - The Free Dictionary
1,779,715,376 visitors served.
forum mailing list For webmasters
?
New: Language forums
Dictionary/
thesaurus
Medical
dictionary
Legal
dictionary
Financial
dictionary
Acronyms
 
Idioms
Encyclopedia
Wikipedia
encyclopedia
?

asynchronous logic
(redirected from Asynchronous circuit)

   Also found in: Wikipedia 0.01 sec.
asynchronous logic [ā′siŋ·krə·nəs ′läj·ik]
(electronics)
A logic network in which the speed of operation depends only on the signal propagation through the network.

(architecture)asynchronous logic - A data-driven circuit design technique where, instead of the components sharing a common clock and exchanging data on clock edges, data is passed on as soon as it is available. This removes the need to distribute a common clock signal throughout the circuit with acceptable clock skew. It also helps to reduce power dissipation in CMOS circuits because gates only switch when they are doing useful work rather than on every clock edge.

There are many kinds of asynchronous logic. Data signals may use either "dual rail encoding" or "data bundling". Each dual rail encoded Boolean is implemented as two wires. This allows the value and the timing information to be communicated for each data bit. Bundled data has one wire for each data bit and another for timing. Level sensitive circuits typically represent a logic one by a high voltage and a logic zero by a low voltage whereas transition signalling uses a change in the signal level to convey information. A speed independent design is tolerant to variations in gate speeds but not to propagation delays in wires; a delay insensitive circuit is tolerant to variations in wire delays as well.

The purest form of circuit is delay-insensitive and uses dual-rail encoding with transition signalling. A transition on one wire indicates the arrival of a zero, a transition on the other the arrival of a one. The levels on the wires are of no significance. Such an approach enables the design of fully delay-insensitive circuits and automatic layout as the delays introduced by the layout compiler can't affect the functionality (only the performance). Level sensitive designs can use simpler, stateless logic gates but require a "return to zero" phase in each transition.

http://cs.man.ac.uk/amulet/async/.


How to thank TFD for its existence? Tell a friend about us, add a link to this page, add the site to iGoogle, or visit webmaster's page for free fun content.
?Page tools
Printer friendly
Cite / link
Email
Feedback
? Mentioned in ? References in periodicals archive
 
The announcement is significant because it demonstrates integration of synchronous and asynchronous circuits in a complex, high-speed device.
Fulcrum Microsystems, a pioneer in asynchronous circuit design (clockless chips), is a fabless semiconductor company that is leveraging its patented Delay-Insensitive design methodology to develop clockless system-on-chip (SOC) solutions that offer significant advantages in power, performance and time to market over those designed using traditional synchronous VLSI design methods.
It automatically computes reset sequences and also proves the equivalence of synchronous and asynchronous circuits.
 
Encyclopedia browser? ? Full browser
 
 
Encyclopedia
?

Disclaimer | Privacy policy | Feedback | Copyright © 2009 Farlex, Inc.
All content on this website, including dictionary, thesaurus, literature, geography, and other reference data is for informational purposes only. This information should not be considered complete, up to date, and is not intended to be used in place of a visit, consultation, or advice of a legal, medical, or any other professional. Terms of Use.