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bit error rate |
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The Agilent N5431A software complements the other Agilent solutions for XAUI testing, including physical layer test systems (PLTS) software for XAUI backplane characterization, digital communication analyzers for optical and electrical transmitter testing, and bit error ratio testers for receiver testing and characterization for parallel stimulus and analysis of XAUI devices. ChipScope Serial I/O toolkit provides an internal bit error ratio tester (IBERT) core that can be placed in the FPGA, along with a JTAG infrastructure enabled by the Xilinx programming cables. The new BERTScope S Pattern Generator allows design and test engineers to generate calibrated, stressed data for jitter tolerance testing when either the device under test or a legacy BERT are used to measure bit error ratio. |
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