bit error rate

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Bit Error Rate

(data, digital, communications)
(BER) The fraction of a message or block of data that is wrong.

bit error rate (BER)

The number of bit errors in a sample divided by the total number of bits in the sample, generally averaged over many such samples (ICAO).
References in periodicals archive ?
The Agilent N21xxB PXIT modular family with the combined bit error ratio tester (BERT) and digital communication analyzer (DCA) is available now at a starting price of $80,000.
The embedded core transmits and receives serial IO signals using a built-in pattern generator and pattern detector to measure bit error ratios with resulting data displayed in real time.
NYSE:A) today announced it has added bit error ratio (BER) capabilities to its optical modulation analyzer.
In addition to quickly and easily testing semiconductors, circuit boards and entire systems, ASSET's ScanWorks system can access embedded instrumentation to control advanced high-speed tests like signal integrity analysis, bit error ratio testing (BERT), pattern generation testing and others.
3bs Task Force will extend Ethernet to 400Gb/s, while improving the bit error ratio to 10-13.
today introduced the new M8000 Series BER test solution, a highly integrated and scalable bit error ratio test solution for physical-layer characterization, validation and compliance testing for receivers used in multigigabit digital designs.
New chapters address handset and high-power power amplifiers, bit error ratio testing, broadband cable, WiMAX, and heterojunction bipolar transistors.
NYSE: A) today announced it will demonstrate a 32-Gb/s bit error ratio tester with fast rise time and higher output amplitude at DesignCon (Booth 201) in Santa Clara Convention Center, Jan.
Engineers must understand how their transmitters, channels, and links affect PAM4 eye quality, and quantify the degree of eye closure due to timing jitter and noise as a function of bit error ratio (BER).
A high-performance Infiniium DSO90000 X-Series oscilloscope will be used to make measurements from the high-speed J-BERT N4903B Bit Error Ratio Tester, at the USB 3.
NYSE: A) today announced it will demonstrate a 32-Gb/s bit error ratio tester at ECOC (Amsterdam RAI, Hall 1, Stand 712) in Amsterdam, Sept.
The IDT M690SDM's performance specifications meet the low bit error ratio (BER) requirements for today's high speed 40G and 100G board designs used in telecommunications and optical networking applications, helping to drive the development of next generation cloud computing and 4G wireless infrastructure.