cache coherency

Managing a cache so that data are not lost or overwritten. For example, when data are updated in a cache, but not yet transferred to its target memory or disk, the chance of corruption is greater. Cache coherency is obtained by well-designed algorithms that keep track of the cache. It is even more critical in symmetric multiprocessing (SMP) where memory is shared by multiple processors. See cache and SMP.

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(storage)

cache coherency - (Or "cache consistency") /kash koh-heer'n-see/ The synchronisation of data in multiple caches such that reading a memory location via any cache will return the most recent data written to that location via any (other) cache. Some parallel processors do not cache accesses to shared memory to avoid the issue of cache coherency. If caches are used with shared memory then some system is required to detect when data in one processor's cache should be discarded or replaced because another processor has updated that memory location. Several such schemes have been devised.