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Chip Scale Packaging

   Also found in: Wikipedia 0.01 sec.
(hardware)Chip Scale Packaging - (CSP) A type of surface mount integrated circuit packaging that provides pre-speed-sorted, pre-tested and pre-packaged die without requiring special testing. An example is Motorola's Micro SMT packaging.

See also: chip-on-board, flip chip, multichip module, known good die, ball grid array.

["Chip scale packaging gains at SMI. (Surface Mount International)", Bernard Levine, Electronic News (1991), Sept 4, 1995 v41 n2081 p1(2)].


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In addition to contracts from graphic-chip vendors, contracts for 65nm wafer-level chip scale packaging capacity from wireless chip designers like Broadcom and CSR are also swarming to the two chip assemblers, further tightening supplies of wafer-bump capacity at the two companies.
Unitive opened a new Die Level Processing (DLP) facility in the United States representing the industry's most advanced turnkey chip scale packaging capability.
INTRODUCTION, METHODOLOGY & PRODUCT DEFINITIONS Study Reliability and Reporting Limitations I-1 Disclaimers I-2 Data Interpretation & Reporting Level I-2 Quantitative Techniques & Analytics I-3 Product Definitions and Scope Of Study I-3 Ball Grid Arrays I-3 Chip Scale Packaging (CSP) I-3 Multi Chip Modules (MCM) I-3 II.
 
 
 
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