chip package


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chip package

The housing that chips come in for plugging into (socket mount) or soldering onto (surface mount) the printed circuit board. Creating a mounting for a chip might seem trivial to the uninitiated, but chip packaging is a huge and complicated industry. The ability to provide more and more I/O interconnections to a die (bare chip) that is increasingly shrinking in size is an ever-present problem. In addition, the smaller size of the package contributes as much to the miniaturization of cellphones and other handheld devices as the shrinking of the semiconductor circuits. See BGA, CDIP, CERDIP, CERQUAD, CLCC, DIP, flatpack, package on package, PLCC, QFP, MCM, MCP, SOP, SOIC, SOJ, TSOP and ZIP.
References in periodicals archive ?
Plastic laminate chip packages are gaining wider acceptance in the semiconductor industry for advanced chip packaging applications, particularly for high pin count and fast clock speed semiconductor packages.
XinTec Wafer Level CSP is a mainstream wafer level packaging technique, offering key advantages over conventional chip packages such as miniaturized and reliable design, increased functionality and board capacity, lower cost and enhanced quality for applications in cellular phones, PDAs, still cameras and other electronic devices.
In the past twelve months, Amkor has delivered over 10 million flip chip packages containing 90nm Common Platform silicon from multiple foundries for the gaming market.