clock pulse


Also found in: Acronyms.

clock pulse

A signal used to synchronize the operations of an electronic system. Clock pulses are continuous, precisely spaced changes in voltage. See clock speed.
References in periodicals archive ?
The input signal (Q1) varies during the clock pulse width due to this reason the second latch has an uncertain output signal(Q2).
A clock pulse may arrive before the inductor current reaches the [I.
Shorted LED detection can be started with two clock pulses during error detection mode while the output port is turned on.
These are computed in a single clock pulse taking advantage of inherent parallelism provided by an FPGA.
In case of first type, synchronization is achieved by applying clock pulses thus ensuring the gate to transmit input signal only that coincide with the arrival of clock pulses.
5usec conversion time with independent (even simultaneous) operation for each unit) SH7083F, SH7084F, SH7085F: 8 channels (4 channels x 2 units) SH7086F: 16 channels (4 channels x 2 units + 8 channels x1 unit) Serial communication interface (SCI) x 4 channels Synchronous serial communication unit (SSU) x 1 channel I2C bus interface x 1 channel Compare-match timer (CMT) x 2 channels Direct memory access controller (DMAC) x 4 channels Data transfer controller (DTC) Interrupt controller (INTC): 9 external interrupts Watchdog timer (WDT) Clock pulse generator (CPG) with built-in multiplication PLL Package 100-pin 112-pin 144-pin 144-pin 176-pin TQFP LQFP LQFP LQFP LQFP Note: I2C (Inter IC Bus) is an interface specification proposed by Royal Philips Electronics of the Netherlands.
In a TIA, sampling is asynchronous as it is in a DSO, but the leading-edge 50% point of a pulse starts an interpolation timer that directly measures the time from the leading edge of the pulse to the next clock pulse.
Like the MC100LVEP111, the NBSG111's synchronous enable feature is used to avoid a runt clock pulse when the device is enabled or disabled -- a common occurrence with an asynchronous control.
Two selectable signals are chosen through a control pin to the MUX; the operation of the output signals can be enabled or disabled, and synchronized with the input signal to eliminate the potential for a runt clock pulse.
The chip also has a 12-channel 10-bit analog-to-digital converter (ADC), 4-channel 8-bit digital-to-analog converter (DAC), clock pulse generator (CPG) with phase-locked-loop (PPL), and a 3-channel serial communication interface (SCI) with IrDA and serial bus capabilities.
They include system timers, a watchdog timer, memory management unit (MMU), clock pulse generator with phase locked loop (PLL) and power-down modes, interrupt controller (INTC), direct memory access controller (DMAC) and bus-state controller (BSC).
0B active specification: FULL CAN support, 32 message buffers) Watchdog timer (WDT) Interrupt controller (INTC): 9 external sources, 115 internal sources User break controller (UBC) User debug interface (H-UDI) Advanced user debugger (AUD) I/O ports: 149 Clock pulse generator: Built-in multiplication PLL (x4, x8) Built-in crystal oscillator halt detection function Power-down modes 3 modes: Sleep, Hardware Standby, Software Standby Power down function: Module Standby Package 256-pin QFP (28mm x 40mm, 0.