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Column Address Strobe

   Also found in: Acronyms 0.01 sec.
(hardware)Column Address Strobe - (CAS) A signal sent from a processor (or memory controller) to a dynamic random-access memory (DRAM) (qv) circuit to indicate that the column address lines are valid.


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The device supports a column address strobe latency (CL) of CL 3 with sequential or interleaved data bursts in lengths of 1, 2, 4, or 8 bits for each data pin and has an access time of 5.
Mitsubishi's 256-Mbit DDR SDRAM is available in 64-megaword x 4-bit (64M x 4) and 32M x 8 configurations (M2S56D20TP and M2S56D30TP, respectively), and supports column address strobe latencies (CL) of CL 1.
5-ns clock cycle operation supports a Column Address Strobe (CAS) Latency of 3.
 
 
 
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