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cycle stealing |
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A CPU design technique that periodically "grabs" machine cycles from the main processor usually by some peripheral control unit, such as a DMA (direct memory access) device. In this way, processing and peripheral operations can be performed concurrently or with some degree of overlap. See also peer-to-peer computing. How to thank TFD for its existence? Tell a friend about us, add a link to this page, add the site to iGoogle, or visit webmaster's page for free fun content. |
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The tool's flexibility supports a wide variety of design styles, including multiple clocks (both edge-triggered and level-sensitive) with cycle stealing. The Fujitsu SPARClite ISS model will support all major functional capabilities of the SPARClite processor, including cache hits/misses for instruction and data cache, cycle counts, burst mode, write buffer, pre- fetch, and cycle stealing. The timing analyzer handles such functions as multi-clock, multi-phase, multi-cycle, false path, cycle stealing, and transparent latch. |
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cycle stealing
