DPLL


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DPLL

Digital Phase-Locked Loop
References in periodicals archive ?
Zarlink's frequency DPLL synthesis technique effectively filters low-frequency phase noise, permitting designers to focus the APLL on its core attribute - eliminating high-frequency phase noise.
The ZL30105 chip is a simple-to-use Stratum 3/4/4E SDH DPLL and includes ITU-T (International Telecommunications Union-Telecommunications) G.
The strength of consistency achieved by the unit propagation rule is reflected in the DPLL performance in many problems.
Hitless reference switching--if the reference the DPLL is locked to fails, the DPLL will lock to another available reference without phase disturbances at its output.
Microsemi's ZL30343 SyncE and IEEE 1588 packet synchronizer, part of the ZL3034x family of DPLLs, which provide all required clock synthesis and network timing functions for a central timing card or line card in carrier grade network equipment.
Dual DPLL architecture, with four reference inputs (single-ended or differential) going to an input crosspoint
With its multicycle phase detector, the T0 DPLL can direct-lock to a number of common telecom frequencies even in the presence of significant jitter and wander on the reference clock.
Each of the DPLLs on the ZL30161, ZL30162 and ZL30163 can be configured to perform as numerically controlled oscillators (NCOs) to recover a clock based on packet-based timing protocols such as IEEE1588 that can be used for GSM, WCDMA and LTE applications.
Our extremely accurate signal path and DPLL architecture eliminate the trade-offs and complexity of previous solutions to provide superior images and improved video quality for high-resolution monitors, projectors and televisions.
Other features include: -- Support for three modes of operation: free-run, holdover and locked -- Integration of input clock selector, local oscillator, DPLL, APLL, and microprocessor for a single stratum 3 synchronization solution -- On board oven-controlled crystal oscillator (OCXO) exceeds clock performance criteria of Telcordia GR-1244 -- Two synchronized outputs up to 77.
The chip defaults to asynchronous free-run mode, where the DPLL generates an output clock with frequency accuracy equal to an external oscillator or low-cost crystal.
Traditional transmitter back-end building blocks made available to Altera customers include pulse-shaping FIRs, a reference-tracking DPLL, resampling interpolators, and an up converter.