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DPLL

   Also found in: Acronyms, Wikipedia 0.02 sec.
DPLL - Digital Phase-Locked Loop


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The T4 DPLL is typically used to convert incoming SONET/SDH clocks into derived DS1 or E1 clocks, which are sent to an external BITS/SSU through one or both of the on-chip DS1/E1 transmitters.
Flexible, Single-Chip SONET/SDH Timing-Card IC From Dallas ... by Business Wire
The integrated DPLL provides N*64KHz clock generation and eliminates the need for an external clock source.
Mindspeed Announces Industry's First Multi-Mode, Voice-Pair Gain ... by Business Wire
Our extremely accurate signal path and DPLL architecture eliminate the trade-offs and complexity of previous solutions to provide superior images and improved video quality for high-resolution monitors, projectors and televisions.
Xicor Introduces the World's Fastest Analog Front End for Flat Panel ... by Business Wire
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