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DRAM refresh

    0.23 sec.
(storage)DRAM refresh - The operation which cycles through a DRAM reading each row and writing it back again to compensate for the gradual leakage of charge from the capacitors which store the data. This may be done by the CPU but is often done by a dedicated memory controller.


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The NxMC controller also incorporates advanced performance features including dual address read prefetching, deep write buffers, ROM shadowing, and hidden DRAM refresh.
NexGen Shipping NxPCI Logic Chipset And Motherboards With Up To 25% ... by Business Wire
The 302 contains a RISC-based communications processor and system integration circuitry, including an independent DMA controller, two general purpose timers/counters, a clock generator, DRAM refresh support, an interrupt controller, parallel output/input (I/O) ports and chip selects.
Motorola announces three derivatives of popular 68302 communications ... by Business Wire
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