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DRAM refresh

    0.03 sec.
(storage)DRAM refresh - The operation which cycles through a DRAM reading each row and writing it back again to compensate for the gradual leakage of charge from the capacitors which store the data. This may be done by the CPU but is often done by a dedicated memory controller.
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The Innovasic processors have the same set of peripherals as the Intel([R]) devices, including the standard numeric interface, interrupt control unit, chip-select unit/Ready Generation Logic, DRAM refresh control unit, power management unit, three 16-bit timer/counters, and two independent DMA channels.
Innovasic Semiconductor Announces the Availability of Pin-Compatible ... by Business Wire
The Innovasic processors have the same set of peripherals as the Intel([R]) devices, including the standard numeric interface, interrupt control unit, chip-select unit/Ready Generation Logic, DRAM refresh control unit, power management unit, three 16-bit timer/counters, and two independent DMA channels.
Innovasic Semiconductor(R) to Produce Pin-Compatible 80C186XL and ... by Business Wire
The Innovasic processors have the same set of peripherals including the standard numeric interface, interrupt control unit, chip-select unit, DRAM refresh control unit, power management unit, three 16-bit timer/counters, and two integrated serial ports supporting both synchronous and asynchronous communications.
Innovasic Semiconductor(R) Announces Production of Pin Compatible ... by Business Wire
 
 
 
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