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DRAM refresh |
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The NxMC controller also incorporates advanced performance features including dual address read prefetching, deep write buffers, ROM shadowing, and hidden DRAM refresh. The 302 contains a RISC-based communications processor and system integration circuitry, including an independent DMA controller, two general purpose timers/counters, a clock generator, DRAM refresh support, an interrupt controller, parallel output/input (I/O) ports and chip selects. |
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