DRAM refresh

DRAM refresh

(storage)
The operation which cycles through a DRAM reading each row and writing it back again to compensate for the gradual leakage of charge from the capacitors which store the data. This may be done by the CPU but is often done by a dedicated memory controller.
References in periodicals archive ?
The contributors assess the impact of DRAM refresh on task execution times, define the temporal interface of a task pipeline by demand bound functions, and simplify execution time distributions via random sampling.
The NxMC controller also incorporates advanced performance features including dual address read prefetching, deep write buffers, ROM shadowing, and hidden DRAM refresh.
The Innovasic processors have the same set of peripherals as the Intel([R]) devices, including the standard numeric interface, interrupt control unit, chip-select unit/Ready Generation Logic, DRAM refresh control unit, power management unit, three 16-bit timer/counters, and two independent DMA channels.
The Innovasic processors have the same set of peripherals including the standard numeric interface, interrupt control unit, chip-select unit, DRAM refresh control unit, power management unit, three 16-bit timer/counters, and two integrated serial ports supporting both synchronous and asynchronous communications.