# Frequency Divider

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## frequency divider

[′frē·kwən·sē di‚vīd·ər]
(electronics)
A harmonic conversion transducer in which the frequency of the output signal is an integral submultiple of the input frequency. Also known as counting-down circuit.

## Frequency Divider

an electronic device that reduces by an integral factor the frequency of periodic oscillations supplied to it. Frequency dividers are used in frequency synthesizers, in quartz-crystal and atomic clocks, in television apparatus (to synchronize scanning generators), and as timing devices in radar. Electronic counters, self-excited sine-wave generators, regenerative devices, self-excited oscillators with phase-locked frequency control, and relaxation generators are used to divide frequencies.

In a self-excited sine-wave generator, frequency division is achieved by synchronizing the generator’s frequency with a subharmonic oscillation of the frequency of the external periodic signal by means of the locking effect. In a regenerative frequency divider for sine waves, the periodic signal of frequency f, which is to be divided, and a signal of frequency (k - 1)·flk (where k is the scaling ratio), which is produced in the feedback circuit only when a voltage of the frequency being converted is fed to the input of the frequency divider, are fed to the frequency converter. The difference-frequency signal, equal tof/k, is obtained at the converter’s output. In apparatus consisting of a self-excited oscillator with phase-locked frequency control, a phase detector compares the frequency of a harmonic oscillation k times greater than the fundamental frequency of the oscillator with the divided frequency. An error voltage from the output of the phase detector, which is proportional to the difference between the frequencies being compared, is fed to the oscillator and varies its frequency until the divided frequency becomes exactly k times smaller. To divide the repetition rate of the pulse signals, relaxation generators are used as frequency dividers. These generators (multivibrators and blocking oscillators) operate in the periodic mode, with the pulse-repetition rate locked onto a subharmonic frequency, or in the driven mode, with a pulse-repetition period k times higher. In practice k does not exceed 10.

### REFERENCES

Frolkin, V. T. Impul’snye ustroistva, 2nd ed. Moscow, 1966.
Gonorovskii, I. S. Radiotekhnicheskie tsepi i signaly, part 2. Moscow, 1967.

IU. B. LIUBCHENKO

References in periodicals archive ?
511 frequency divider based on ETSPC and TSPC logic flip-flops in 65 nm CMOS technology.
However this drop of power is not considered as a problem, because the minimum power level is still in the range of power accepted for the frequency divider.
By applying my musical sense of circuit behavior, I was able to find regions on the manifold for which the Chua circuit behaved almost exactly as my chaotic frequency dividers had twenty-seven years earlier.
Huang, "LC-tank Colpitts injection-locked frequency divider with even and odd modulo," IEEE Microw.
For the most part, frequency dividers are used in a phase-locked loop (PLL) to divide the voltage-controlled oscillator (VCO) output frequency down to the reference frequency in order to achieve phase/frequency locking.
The MG-7050 family integrates a complete timing chain - a SAW oscillator, frequency dividers, and fan-out buffers - and still achieves the same jitter performance as Epson's industry-leading XG-2121 and XG-2102 series of SAW oscillators.
The frequency divider converts the input signal at a given frequency to a new frequency based on the ratio of the frequency divider, N.
This work eliminates the use of frequency dividers, which reduces chip size, power consumption and cost.
Sometimes for certain drive levels and input frequencies the amplifier may turn into an oscillator (self-oscillating mixer) or, more often, a frequency divider.
Many analog frequency divider circuits were invented during the age of the vacuum tube.
A K-band static frequency divider ([divided by] 128) implemented with an inductively peaked input buffer at the left side is shown in Figure 9;[8] its response is shown in Figure 10.
Static fractional division consists of a frequency multiplier and a programmable frequency divider with unity steps, as shown in Figure 2.

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