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High-K/Metal Gate

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High-K/Metal Gate

The technology in an Intel chip that enabled the fabrication of 45 nm microprocessors in 2007. As elements in the chip were being reduced to 45 nanometers, the gate dielectric began to lose its insulating (dielectric) quality and exhibited too much leakage. The gate dielectric is a very thin insulation layer, traditionally made of silicon dioxide, that lies between the transistor's metal gate electrode and the channel through which the current flows.

Intel's solution to the problem was to combine a hafnium-based dielectric layer, instead of silicon dioxide, with a gate electrode composed of alternative metal materials. The resulting combination yields a "high dielectric constant," otherwise known as a "high-K." See transistor.



Electrode and Dielectric
When the gate is pulsed, current flows between the source and drain. Intel's High-K/Metal Gate technology enabled elements on a chip to be reduced to 45 nm with stability. SiGe stands for silicon germanium. (Bottom image courtesy of Intel Corporation.)



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SEMATECH has been at the forefront of advanced transistor development, demonstrating high-k/metal gate stacks that can be used to build high-performance nMOS and pMOS transistors in a CMOS configuration.
The new data, available in detail to member companies only, follows SEMATECH's announcement in January of high-k/metal gate stacks that were used to build high-performance nMOS and pMOS transistors in a CMOS configuration.
The Tempus HPC Platform of products and services currently includes a Fluids Line for applications including self-assembly, surface preparations and cleans processes and electroless deposition, and a Physical Vapor Deposition Line for applications including non-volatile memory, high-k/metal gate and advanced interconnect.
 
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