Hybrid Memory Cube


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Hybrid Memory Cube

A memory module technology from the Hybrid Memory Cube Consortium (HMCC), spearheaded by Micron and Samsung, that stacks chips vertically rather than horizontally. Finalized in 2013, Hybrid Memory Cubes (HMCs) provide 15 times the bandwidth of DDR3 chips while consuming 70% less power and 90% less space. Like DRAM, HMCs lose their content without power.

Initially used in supercomputers and high-speed servers, HMC memory is expected to migrate to all types of computing devices. See dynamic RAM, memory module and via.


3D Stacking
DRAM layers are stacked over a logic layer and connected with "vias" (corner cutout) that run through the silicon. This compact architecture is faster and more energy efficient than conventional DRAM modules. (Image courtesy of the HMC Consortium, www.hybridmemorycube.org)
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Hybrid Memory Cube uses a stacked memory chip configuration, forming a compact "cube," and uses a new, highly efficient memory interface which sets the bar for energy consumed per bit transferred while supporting data rates of one trillion bits per second.
New development boards include the Xilinx Kintex UltraScale(TM) KCU105 Evaluation Kit, the Micron Pico Computing SB-850 board with support for Hybrid Memory Cube (HMC), the Alpha Data ADM-PCIE-KU3 board and the 4DSP CES820 commercial-off-the-shelf (COTS) compact embedded system.
today announced they have jointly demonstrated successful interoperability between Altera StratixA V FPGAs and Micron s Hybrid Memory Cube (HMC).
NASDAQ: CDNS), a leader in global electronic design innovation, today announced the immediate availability of verification IP (VIP) supporting all popular 3D memory standards including Wide I/O 2, Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM) and DDR4 3D Stacking (DDR4-3DS).
FPGA Interoperability with Micron's Hybrid-Memory Cube This demonstration shows the interoperability between Stratix V FPGAs and Micron's Hybrid Memory Cube (HMC).