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HyperTransport |
Also found in: Wikipedia | 0.02 sec. |
HyperTransportA high-speed interconnection architecture between integrated circuits, introduced in 2001. Code named Lightning Data Transport and developed by AMD and others, the HyperTransport I/O Link Specification defines a protocol and electrical interface between the CPU, memory and peripheral devices.
HyperTransport Version
Feature HT 1.x HT 2.0 HT 3.0
Year introduced 2001 2004 2006
Max clock speed 800 MHz 1.4 GHz 2.6 GHz
Max bandwidth (GB/sec) 12.8 22.4 41.6
Hot pluggable No No Yes
Un-Ganging No No Yes
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| ? Mentioned in | ? References in periodicals archive | |
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Up to four PCI Express X8 channels and four 1Gbps Ethernet links are supported through dual ServerWorks Hyper Transport 2000 chipsets, which together provide up to 4GB of bidirectional I/O. 5 includes significant productivity and technology enhancements targeted at emerging SERDES interconnect standards such as PCI-Express, Hyper Transport, XAUI and SATA/SAS. Hyper Transport Consortium -- VMETRO -- LeCroy Corporation -- Wavecrest -- Mentor Graphics |
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