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A high-speed interconnection architecture between integrated circuits, introduced in 2001. Code-named Lightning Data Transport and developed by AMD and others, the HyperTransport I/O Link Specification defines a protocol and electrical interface between the CPU, memory and peripheral devices.

Since its introduction, HyperTransport's maximum aggregate bandwidth of 32-bit links progressed from 12.8 to 41.6 Gbytes/sec. Version 3.0 also added dynamic link splitting under software control. Called "Un-Ganging," it enables a single unidirectional link to be split into two; each at half the original bit width. HyperTransport (HT) was designed to be fully compatible with legacy PCI (running at 33 or 66 MHz) plus PCI Express and PCI-X technologies. For more information, visit the HyperTransport Consortium at www.hypertransport.org.
HYPERTRANSPORT VERSION               HT 1.x   HT 2.0   HT 3.0Feature        (2001)   (2004)   (2006)

 Clock speed    800 MHz  1.4 GHz  2.6 GHz

  (GB/sec)       12.8     22.4     41.6

 Hot pluggable   No       No       Yes

 Un-Ganging      No       No       Yes
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References in periodicals archive ?
The HyperTransport Technology Consortium is a non-profit organization managed by its members that is dedicated to promoting HyperTransport technology as an open, freely available industry specification for high bandwidth chip-to-chip communications.
HyperTransport technology is a high-speed, high-performance, point-to-point link for integrated circuits.
Xilinx is using the HT8000 platform for hardware validation and interoperability testing of our own HyperTransport cores.
The GDA Technologies HT8000 HyperTransport Compatibility Platform is a 12.
The HyperTransport[TM] Technology Consortium, a non-profit organization dedicated to developing, promoting and licensing the industry's lowest latency, highest bandwidth interconnect technology, today announced that Dell has joined the consortium as a high-level member and will leverage HyperTransport technology in a number of its powerful server and desktop product lines.
HyperTransport interconnect technology is an innovative solution that moves information faster, enabling the chips inside of PCs, networking and communications devices to communicate with each other up to 48 times faster than with existing technologies.
Providing a forum for members to learn more about the industry's highest performance interconnect technology, the HyperTransport[TM] Technology Consortium today announced that its annual HyperTransport Technology Developers Conference will take place on Thursday, October 16, 2008, at the Santa Clara Marriott Hotel in Santa Clara, Calif.
The HTX Connector specification defines the electrical and mechanical characteristics of an EATX motherboard interface connector, enabling CPUs to connect directly via a HyperTransport link to add-in card subsystems requiring HyperTransport's state-of-the-art low latency and bandwidth.
a fast growing supplier of Intellectual Property and Design Services, today announced the availability of a comprehensive set of HyperTransport IP cores for ASIC integration and FPGA-based solutions.
Further extending the capabilities of the industry's highest performance, lowest latency interconnect technology, the HyperTransport[TM] Technology Consortium (HTC) today released the HyperTransport 3.