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HyperTransport

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HyperTransport

A high-speed interconnection architecture between integrated circuits, introduced in 2001. Code named Lightning Data Transport and developed by AMD and others, the HyperTransport I/O Link Specification defines a protocol and electrical interface between the CPU, memory and peripheral devices.

Since its introduction, HyperTransport's maximum aggregate bandwidth of 32-bit links progressed from 12.8 to 41.6 Gbytes/sec. Version 3.0 also added dynamic link splitting under software control. Called "Un-Ganging," it enables a single unidirectional link to be split into two; each at half the original bit width. HyperTransport (HT) was designed to be fully compatible with legacy PCI (running at 33 or 66 MHz) plus PCI Express and PCI-X technologies. For more information, visit the HyperTransport Consortium at www.hypertransport.org.


                         HyperTransport Version
 Feature                 HT 1.x   HT 2.0   HT 3.0

 Year introduced         2001     2004     2006

 Max clock speed         800 MHz  1.4 GHz  2.6 GHz

 Max bandwidth (GB/sec)  12.8     22.4     41.6

 Hot pluggable           No       No       Yes

 Un-Ganging              No       No       Yes



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Schlumberger Semiconductor Solutions, a business unit of Schlumberger Limited (NYSE:SLB), recemtly announced that AMD (NYSE:AMD) has purchased the ITS9000ZX system, a high performance system that will be used to test the HyperTransport I/O Link data bus technology.
There are still other new architectures in development, including the AMD-backed HyperTransport I/O specification.
AMD (NYSE:AMD) has announced that NVIDIA has incorporated AMD's HyperTransport data bus technology into its new nForce platform processing architecture, becoming the first chipset to incorporate AMD's innovative data bus technology.
 
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