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pipelining |
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pipelining [′pīp‚līn·iŋ] (computer science) A procedure for processing instructions in a computer program more rapidly, in which each instruction is divided into numerous small stages, and a population of instructions are in various stages at any given time.
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The APU controller provides a flexible high-bandwidth interface between the reconfigurable logic in the FPGA fabric and the instruction pipeline of the integrated IBM PowerPC(TM) 405 CPU. In a pioneering move to maximize clock utilization, the MAXQ does not implement an instruction pipeline to support its 1-cycle operation. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million instructions per second (MIPS) at a clock rate of 25 MHz. |
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