instruction set

(redirected from Instruction set architectures)

instruction set

[in′strək·shən ‚set]
(computer science)
Also known as instruction repertory.
The set of instructions which a computing or data-processing system is capable of performing.
The set of instructions which an automatic coding system assembles.

instruction set

(architecture)
The collection of machine language instructions that a particular processor understands.

The term is almost synonymous with "instruction set architecture" since the instructions are fairly meaningless in isolation from the registers etc. that they manipulate.

instruction set

The group of machine language instructions that a computer can follow, which may range from a handful to several hundred. It is a fundamental architectural component of a CPU and is either built into the CPU or into microcode, a layer between the instruction set and the circuitry. The instruction length is generally from one to four bytes long. See CISC, RISC, machine language, microcode and CPU.
References in periodicals archive ?
NASDAQ: MIPS) has announced a major release of the MIPS(R) architecture, encompassing the MIPS32(R), MIPS64(R) and microMIPS instruction set architectures.
Its anti tamper solutions are based on its TrustGUARD security processors that pioneered the concept of random instruction set architectures that are unique for each device.
MIPS SDE supports MIPS32[R] and MIPS64[R] Instruction Set Architectures (ISAs), including the MIPS32[R]4K([R]), 24K([R]), and 34K[TM] processor cores, and runs on PC Linux, Windows, and Sun Solaris operating systems.
Since the dawn of the computer era, the need for binary compatibility with instruction set architectures and operating system interfaces has locked users into proprietary environments.
To date LSI Logic has licensed a number of products from MIPS Technologies including the MIPS32 and MIPS64(R) instruction set architectures and processor cores from the 4KE(TM) and 5K(TM) core families.
The MIPS SDE supports all current variations of the MIPS architecture, including MIPS Technologies' MIPS32(TM) and MIPS64(R) Instruction Set Architectures plus the MIPS16e(TM), SmartMIPS(TM) and MIPS-3D(TM) extensions.
The new gate-count estimator gives real-time feedback to software designers unfamiliar with hardware development, allowing them to explore various embedded processor instruction set architectures while receiving immediate feedback on the cost implications of their extended-instruction choices.
The simulation model was developed using AXYS Design's MaxCore(R) tool and the processor description in C-based Language for Instruction Set Architectures (LISA).
MDIserver is available for both the ARM and MIPS Instruction Set Architectures and supports Linux and Solaris host systems.
Transitive Technologies today announced the availability of Dynamite(TM) X/M, the first CPU translation and optimization software engine that enables software written for legacy x86-based platforms to run transparently on the patented, industry-standard MIPS32(TM) and MIPS64(TM) instruction set architectures (ISAs).
The company's HotShot(TM) Technology provides a silicon-based, JIT (Just-in-Time) translation and optimization platform for open software environments, media streams and instruction set architectures.
As part of the agreement, the companies will combine engineering and marketing resources to facilitate porting, optimization and distribution of Wind River's marketshare leading software, including the Tornado(R) development platform and VxWorks(R) real time operating system, for MIPS Technologies MIPS32(TM) and MIPS64(TM) processor architectures, as well as earlier MIPS Instruction Set Architectures.

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