Instruction set architectures definition of Instruction set architectures in the Free Online Encyclopedia.

instruction set

The group of machine language instructions that a computer can follow, which may range from a handful to several hundred. It is a fundamental architectural component of a CPU and is either built into the CPU or into microcode, a layer between the instruction set and the circuitry. The instruction length is generally from one to four bytes long. See CISC, RISC, machine language, microcode and CPU.

instruction set [in′strək·shən ‚set]

(computer science)

Also known as instruction repertory.

The set of instructions which a computing or data-processing system is capable of performing.

The set of instructions which an automatic coding system assembles.

(architecture)

instruction set - The collection of machine language instructions that a particular processor understands.

The term is almost synonymous with "instruction set architecture" since the instructions are fairly meaningless in isolation from the registers etc. that they manipulate.

Mentioned in	?		References in periodicals archive	?		Encyclopedia browser	?		Full browser	?
No references found	MIPS SDE supports MIPS32[R] and MIPS64[R] Instruction Set Architectures (ISAs), including the MIPS32[R]4K([R]), 24K([R]), and 34K[TM] processor cores, and runs on PC Linux, Windows, and Sun Solaris operating systems. Express Logic's ThreadX(R) RTOS Gains MIPS(R) SDE Kernel-Aware Debug ... by Business Wire Nathan Brookwood, principal analyst, Insight 64 "Since the dawn of the computer era, the need for binary compatibility with instruction set architectures and operating system interfaces has locked users into proprietary environments. Transitive's Breakthrough Hardware Virtualization Products Eliminate ... by Business Wire To date LSI Logic has licensed a number of products from MIPS Technologies including the MIPS32 and MIPS64(R) instruction set architectures and processor cores from the 4KE(TM) and 5K(TM) core families. LSI Logic Licenses Highest Performance MIPS32 24K Processor Core ... by Business Wire	institutional occupancy Institutional Revolutionary Party Institutionalism Instruction instruction address instruction address register instruction area instruction card Instruction Code instruction constant instruction counter instruction cycle Instruction Format instruction length instruction lookahead instruction mix instruction mnemonic Instruction Modification instruction pointer instruction prefetch instruction register instruction repertory instruction scheduling instruction set instruction set architecture Instruction set architectures Instruction Set Processor instruction time instruction transfer instruction word Instructional Literature Instructional Materials Instructional Procedure Instructional Program Instructions From Voters Instructions to a Son instructions to bidders instructions to tenderers Instructor Instrument instrument approach chart instrument approach procedure instrument approach system instrument correction Instrument Errors instrument flight instrument flight regulations instrument flight rules instrument housing instrument landing instrument landing system	Instruction Local Memory Bus instruction lookahead instruction manual instruction manual Instruction Memorandum instruction mix instruction mnemonic instruction modification instruction of partial denture patient instruction of partial denture patient instruction of partial denture patient instruction of partial denture patient Instruction Pamphlet Instruction pipeline Instruction Plate Instruction pointer Instruction pointer Instruction prefetch Instruction Preprocessing Function Instruction Processing Unit Instruction register Instruction register Instruction Removal Detector instruction repertoire instruction repertory Instruction scheduling Instruction set Instruction set Instruction set architecture Instruction set architecture Instruction set architectures Instruction Set Computer Instruction Set Extension Instruction Set Extension Fabric Instruction Set Processor Instruction Set Processor Instruction Set Processor Specification Instruction Set Simulator instruction sets Instruction Space Key Instruction State Queue instruction time instruction to appear Instruction to Bidder Instruction to Contractors Instruction To Defense Instruction to Tenderers instruction transfer Instruction Translation Look-aside Buffer Instruction Type Prediction Table instruction word Instruction, Operation and Maintenance Instruction-Level Distributed Processor Instruction-level parallelism Instruction-Side Processor Local Bus Instruction-Side-On-Chip Memory

Mentioned in

References in periodicals archive

Encyclopedia browser

Full browser

No references found

MIPS SDE supports MIPS32[R] and MIPS64[R] Instruction Set Architectures (ISAs), including the MIPS32[R]4K([R]), 24K([R]), and 34K[TM] processor cores, and runs on PC Linux, Windows, and Sun Solaris operating systems.

Express Logic's ThreadX(R) RTOS Gains MIPS(R) SDE Kernel-Aware Debug ... by Business Wire

Nathan Brookwood, principal analyst, Insight 64 "Since the dawn of the computer era, the need for binary compatibility with instruction set architectures and operating system interfaces has locked users into proprietary environments.

Transitive's Breakthrough Hardware Virtualization Products Eliminate ... by Business Wire

To date LSI Logic has licensed a number of products from MIPS Technologies including the MIPS32 and MIPS64(R) instruction set architectures and processor cores from the 4KE(TM) and 5K(TM) core families.

LSI Logic Licenses Highest Performance MIPS32 24K Processor Core ... by Business Wire

institutional occupancy

Institutional Revolutionary Party

Institutionalism

Instruction

instruction address

instruction address register