Intel Hub Architecture


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Intel Hub Architecture

Intel's architecture for the 8xx family of chipsets, starting with the 820. It uses a memory controller hub (MCH) that is connected to an I/O controller hub (ICH) via a 266 MB/sec bus. The MCH chip supports memory and AGP, while the ICH chip provides connectivity for PCI, USB, sound, IDE hard disks and LAN.

Because of the high-speed channel between the sections, the Intel Hub Architecture (IHA) is much faster than the earlier Northbridge/Southbridge design, which hooked all low-speed ports to the PCI bus. The IHA also optimizes data transfer based on data type. See Northbridge and Intel chipsets.


Intel Hub Architecture
Intel introduced its hub architecture starting with the 820 chipset, which divides control between a memory controller chip (MCH) and an I/O controller chip (ICH). This is an illustration of the 850.
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The new SST49LF003A provides 3 Mbit of flash memory array, which overlays on top of the standard 4 Mbit Firmware Hub memory map partitioning, for storing system BIOS and embedded OS/application software for the Intel Hub Architecture systems.
By incorporating the Intel Hub Architecture, SST's new application-specific flash memory products are designed to complement Intel's 82801 chip, also known as the I/O Controller Hub (ICH), and other Hub devices in the Intel 800 Series Hub Architecture chipsets.
The SST49LF00x Firmware Hub family provides up to 8 Mbit of flash memory array for storing system BIOS and video BIOS for the Intel Hub Architecture systems.