As a synthesizable version of IBM's most popular hard core series, the PowerPC 405S now supports a user-definable L1 cache
size that helps SoC designers optimize performance and area to match the application requirements.
2 GHz), 128 KB L1 cache
, 1 MB L2 cache, 8 GB main memory.
Key features of the updated AMC121 include: Processor -- Intel Core 2 dual-core architecture -- Independent L1 cache
structures per core -- Shared L2 cache (4MB) -- 64-bit processor -- Compatible with existing 32-bit code base -- Enhanced Intel SpeedStep(R) technology for more efficient power management Memory -- Low latency, high bandwidth -- 64-bit DDR2 PC2-3200 -- 200-pin SO-RDIMM -- Supports up to 4 GB DRAM -- ECC checking with double-bit detect and single-bit correct Storage -- Onboard MiniSD card site with program and operating system storage space enables the module to boot without an external connection AdvancedMC Connector Ports -- Port 0: 1 Gb/2.
Based on TI's enhanced TMS320C64x+(TM) core, the C6452 DSP delivers double the L1 cache
memory and 40 percent more L2 cache than the C6415T, giving customers more headroom to easily add differentiating features to their designs.
Dual PowerPC(R) 7457 processors with 64Kbyte L1 cache
, 256Kbyte internal L2 cache and AltiVec(R) technology for fast floating point and vector processing operations
6 GHz, 32 KB L1 cache
, 256 KB L2 cache, 9 MB L3 cache, 256 GB main memory; 160 Application servers 155 Dialog/Update servers: HP Integrity Model rx4640, 4-way SMP, Intel Itanium 2, 1.
8mm ball pitch -- X86 Software Compatibility -- 256-bit VLIW engine with X86 Code Morphing Software -- 192KB L1 cache
(128KB Instruction, 64KB Data) -- 1MB L2 cache -- 900MHz to 1100MHz operating frequencies at very low power levels -- Integrated Northbridge core logic with: -- DDR memory controller -- AGP graphics interface -- HyperTransport I/O bus controller -- Enhanced LongRun(R) power and thermal management technology -- Highly responsive and dynamic control over power and thermal consumption based on workload demands -- Support for MMX, SSE and SSE2 instructions
Both Flash and SRAM have on-chip L1 caches
to further speed processing.
We have speculated that VIA would be better off pursuing the IDT WinChip 4 processor design rather than the Cyrix cores it has acquired, although Cyrix's brand name and bus interface designs, among other Cyrix assets, are also valuable," he said, "the WinChip 4 design uses large L1 caches
(128K total) and no L2 caches, a strategy that sets it apart from Intel and Cyrix, which use smaller L1 caches
(32K total) coupled with separate, larger L2 caches (256K) on their newest chip designs.
The Power4 will have bigger L1 caches
, and will also borrow IBM's "smart caching" L2 cache technology, which first made its debut in the RS/6000 F50 and H50 PowerPC 604e servers.