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front side bus
(redirected from Memory bus)

   Also found in: Wikipedia 0.02 sec.
(hardware)front side bus - (FSB) The bus via which a processor communicates with its RAM and chipset; one half of the Dual Independent Bus, the other half being the backside bus. The L2 cache is usually on the FSB, unless it is on the same chip as the processor In PCI systems, the PCI bus runs at half the FSB speed.

Intel's Pentium 60 processor used a bus speed and processor speed of 60 MHz. All later processors have used multipliers to increase the internal clock speed while maintaining the same external clock speed, e.g. the Pentium 90 used a 1.5x multiplier. Modern Socket 370 motherboards support multipliers from 4.5x to 8.0x, and FSB speeds from 50 MHz to a proposed 83 MHz standard. These higher speeds may cause problems with some PCI hardware.

Altering the FSB speed and the multiplier ratio are the two main ways of overclocking processors.

Toms Hardware - The Bus Speed Guide.

Toms Hardware - The Overclocking Guide.


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This is often the case for a memory bus configured with multiple DLMM modules that needs to have the timing verified across process and for multiple memory vendors.
The problem is the lack of memory bandwidth as well as contention between processors over the memory bus available to each processor-the set of wires used to carry memory addresses and data to and from the system RAM.
Like FPM DRAM, it can only be used on computer systems with memory bus speeds of up to the recommended 66MHz.
 
 
 
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