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front side bus
(redirected from Memory bus)

   Also found in: Acronyms, Wikipedia 0.07 sec.
(hardware)front side bus - (FSB) The bus via which a processor communicates with its RAM and chipset; one half of the Dual Independent Bus, the other half being the backside bus. The L2 cache is usually on the FSB, unless it is on the same chip as the processor In PCI systems, the PCI bus runs at half the FSB speed.

Intel's Pentium 60 processor used a bus speed and processor speed of 60 MHz. All later processors have used multipliers to increase the internal clock speed while maintaining the same external clock speed, e.g. the Pentium 90 used a 1.5x multiplier. Modern Socket 370 motherboards support multipliers from 4.5x to 8.0x, and FSB speeds from 50 MHz to a proposed 83 MHz standard. These higher speeds may cause problems with some PCI hardware.

Altering the FSB speed and the multiplier ratio are the two main ways of overclocking processors.

Toms Hardware - The Bus Speed Guide.

Toms Hardware - The Overclocking Guide.


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Until now, the access rate per channel for memory slots decreased as the memory bus speed increased, limiting density build-up.
Analysis includes timing between signals, inverse assembly and packet display for key buses, as well as time-correlation of protocol packets to CPU and memory bus activity.
The VS2000 feature set includes a 60 MHz 32-bit Lightfoot RISC CPU core, 10/100 Ethernet MAC with a 4KB frame buffer SRAM, external memory controller with 32MB addressing range, configurable 8- or 32-bit external memory bus, glueless interface including four individually-programmed chip selects, two cache controllers, two UARTS, three SPI ports, watchdog timer, real-time clock and interrupt controller.
 
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