PCIe lane

PCIe lane

A channel in the PCI express interface. See PCI Express.
References in periodicals archive ?
Wasting a PCIe lane on additional Ethernet and USB 3.
2 connector that provides fast transfer speeds of up to 32Gb/s, an Intel GbE LAN port with the cFosSpeed Internet Accelerator Software to eliminate lag, and 2-Way graphics support with the x16 PCIe lane coming directly from the processor for a clean and unrestricted bandwidth, allowing the system to be ready for any demanding application or task.
As the smallest, lowest-power bridge on the market today, the PEX 8111 provides highly efficient bridging between a single PCIe lane to the standard 32-bit PCI bus," said Steve Moore, PLX senior marketing manager for bridge products.
It provides a bridge from a single PCIe lane (x1) to the standard 32-bit PCI bus.
The PEX 8111 provides a bridge from a single PCIe lane (x1) to the standard 32-bit PCI bus.
0 lanes, with 128 PCIe lanes available in a dual socket system.
With up to 32 cores (64 threads), 8 memory channels and 128 PCIe lanes, AMD's EPYC processors offer flexibility, performance, and security features for today's software defined ecosystem.
The top of the line TR 1950X competes with the new Core i9-7900X, but it offers more cores, more PCIe lanes and cache.
With dedicated PCIe lanes for cutting-edge USB, graphics, data and other I/O, the AMD AM4 platform will not steal lanes from other devices and components.
0, which provides a faster I/O bus, more PCIe lanes and increased I/O bandwidth, enabling Emulex Gen 5 FC technology to provide optimal performance for applications, such as virtualization and database management systems, by matching the performance capabilities of server platforms based on the new Intel Xeon processor E5-2600 V2 product family.
062") thick add-on cards, the series consists of six connectors with one to 32 high-speed serial PCIe lanes, each matching different bandwidth capabilities.
The new devices double the throughput bandwidth of existing PCIe lanes to 5 gigabits per second of data transfer, allowing a 50% reduction in the number of PCIe lanes and board traces necessary to support link throughput requirements.