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phase-locked loop |
Also found in: Wikipedia | 0.02 sec. |
phase-locked loopSee PLL. phase-locked loop [′fāz ¦läkt ′lüp] (electronics) A circuit that consists essentially of a phase detector which compares the frequency of a voltage-controlled oscillator with that of an incoming carrier signal or reference-frequency generator; the output of the phase detector, after passing through a loop filter, is fed back to the voltage-controlled oscillator to keep it exactly in phase with the incoming or reference frequency. Abbreviated PLL. How to thank TFD for its existence? Tell a friend about us, add a link to this page, add the site to iGoogle, or visit webmaster's page for free fun content. |
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Elimination of internal Phase-Lock Loop (PLL) to dramatically reduce current consumption and eliminate the need for an external clock; In addition, all devices feature an integrated voltage-controlled oscillator (VCO) and phase-lock loop (PLL), as well as an innovative chip design that eliminates channel crosstalk and performs significantly better than the SMPTE jitter specification. In addition, all devices feature an integrated voltage-controlled oscillator (VCO) and phase-lock loop (PLL), as well as an innovative chip design that eliminates channel crosstalk and performs significantly better than the SMPTE jitter specification. |
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