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phase-locked loop |
Also found in: Acronyms, Wikipedia | 0.04 sec. |
phase-locked loopSee PLL. phase-locked loop [′fāz ¦läkt ′lüp] (electronics) A circuit that consists essentially of a phase detector which compares the frequency of a voltage-controlled oscillator with that of an incoming carrier signal or reference-frequency generator; the output of the phase detector, after passing through a loop filter, is fed back to the voltage-controlled oscillator to keep it exactly in phase with the incoming or reference frequency. Abbreviated PLL. How to thank TFD for its existence? Tell a friend about us, add a link to this page, add the site to iGoogle, or visit webmaster's page for free fun content. |
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AIX-EN-PROVENCE, France -- Peregrine Semiconductor, a supplier of the industry's most advanced RF CMOS integrated circuits, today announced that its European subsidiary, Peregrine Semiconductor Europe, has been chosen by the European Space Agency (ESA) to develop the first Phase-Locked Loop (PLL) device for integration into European space applications. 0, a new generation of its successful phase-locked loop (PLL) circuit design and evaluation tool, as well as two new PLL synthesizers delivering industry-leading performance for the upconversion and downconversion of RF signals in wireless base station equipment. The CY23EP05 and CY23EP09 phase-locked loop (PLL) clock buffers offer the highest operating frequency, the lowest cycle-to-cycle jitter and the lowest output-to-output skew on the market. |
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