PowerPC
A family of RISC-based CPU chips developed by IBM, Motorola and Apple that are based on IBM's POWER chip architecture. The PowerPC family supports a wide range of computing devices from handheld machines to supercomputers. The chips have been used in Apple's Power Macs, various models of IBM's pSeries (RS/6000), certain AS/400 models as well as embedded systems.
IBM owns the designs, and both IBM and Motorola sell the chips. IBM had initially thought to offer the PowerPC as a stand-alone AIX or Windows NT personal computer, but abandoned the project.
PowerPC CPU Technical Specs
Starting in 1993 with the MPC601's 50 MHz clock, PowerPC CPUs have reached gigahertz ratings. Because of the PowerPC's RISC architecture, clock speeds are typically lower than CISC-based CPUs. Therefore, clock speed metrics of Macs and x86-based PCs will not provide a meaningful performance comparison.
Until 2003, all PowerPCs were 32-bit CPUs with internal 64-bit data paths to memory, similar to the Pentium. In 2003, IBM introduced the 64-bit, POWER4-based PowerPC 970, which Apple employed in its G5 Macintoshes.
Faster Multimedia Processing
In 1999, Motorola included the AltiVec vector processor in its model 7400 CPU, which Apple coined the Velocity Engine for its G4 Macintoshes. Similar to Intel's SSE and AMD's 3DNow! instructions, Macintosh graphics and video applications can be updated to take advantage of faster multimedia computations. See G5, POWER, Macintosh and CHRP.
Word
PowerPC Year Size # of Macintosh
Model Intro. (bits) Trans. Models
970 2003 64 52M G5
7400 1999 32 10.5M G4
750 1997 32 6.4M G3
740 1997 32 6.4M G3
604e 1996 32 5.1M
603e 1996 32 2.6M lp**
603 1995 32 1.6M
604 1995 32 3.6M
602 1995 32 1M lp**
601 1993 32 2.8M
lp** = low power for laptops
| (processor, standard) | PowerPC - (PPC) A RISC microprocessor designed
to meet a standard which was jointly designed by Motorola,
IBM, and Apple Computer (the PowerPC Alliance). The
PowerPC standard specifies a common instruction set architecture (ISA), allowing anyone to design and fabricate
PowerPC processors, which will run the same code. The PowerPC
architecture is based on the IBM POWER architecture, used in
IBM's RS/6000 workstations. Currently IBM and
Motorola are working on PowerPC chips.
The PowerPC standard specifies both 32-bit and 64-bit data
paths. Early implementations were 32-bit (e.g. PowerPC 601); later higher-performance implementations were 64-bit
(e.g. PowerPC 620). A PowerPC has 32 integer registers (32-
or 64 bit) and 32 floating-point (IEEE standard 64 bit)
floating-point registers.
The POWER CPU chip and PowerPC have a (large) common core, but
both have instructions that the other doesn't. The PowerPC
offers the following features that POWER does not:
Support for running in little-endian mode.
Addition of single precision floating-point operations.
Control of branch prediction direction.
A hardware coherency model (not in Book I).
Some other floating-point instructions (some optional).
The real time clock (upper and lower) was replaced with the
time base registers (upper and lower), which don't count in
sec/ns (the decrementer also changed).
64-bit instruction operands, registers, etc. (in 64 bit
processors).
See also PowerOpen, PowerPC Platform (PReP).
IBM PPC info.
gopher://info.hed.apple.com/, "Apple Corporate News/"
(press releases), "Apple Technologies/" and "Product
Information/". gopher://ike.engr.washington.edu/, "IBM
General News/", "IBM Product Announcements/", "IBM Detailed
Product Announcements/", "IBM Hardware Catalog/".
Usenet newsgroups: news:comp.sys.powerpc,
news:comp.sys.mac.hardware.
["Microprocessor Report", 16 October 1991]. | |