reduced instruction set computer definition of reduced instruction set computer in the Free Online Encyclopedia.

reduced instruction set computer [ri¦düst in′strək·shən ‚set kəm′pyüd·ər]

(computer science)

A computer in which the compiler and hardware are interlocked, and the compiler takes over some of the hardware functions of conventional computers and translates high-level-language programs directly into low-level machine code. Abbreviated RISC.

(processor)

Reduced Instruction Set Computer - (RISC) A processor whose design is based on the rapid execution of a sequence of simple instructions rather than on the provision of a large variety of complex instructions (as in a Complex Instruction Set Computer).

Features which are generally found in RISC designs are uniform instruction encoding (e.g. the op-code is always in the same bit positions in each instruction which is always one word long), which allows faster decoding; a homogenous register set, allowing any register to be used in any context and simplifying compiler design; and simple addressing modes with more complex modes replaced by sequences of simple arithmetic instructions.

Examples of (more or less) RISC processors are the Berkeley RISC, HP-PA, Clipper, i960, AMD 29000, MIPS R2000 and DEC Alpha. IBM's first RISC computer was the RT/PC (IBM 801), they now produce the RISC-based RISC System/6000 and SP/2 lines.

Despite Apple Computer's bogus claims for their PowerPC-based Macintoshes, the first RISC processor used in a personal computer was the Advanced RISC Machine (ARM) used in the Acorn Archimedes.

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No references found	TAEC) has unveiled a new 32-bit single-chip MIPS-based reduced instruction set computer (RISC) microcontroller (MCU) family. TOSHIBA UNVEILS 32-BIT SINGLE-CHIP MIPS BASED RISC MCU by Electro Manufacturing The TX7901 MIPS reduced instruction set computer (RISC) processor-based AVM79R reference design is a leading-edge evaluation system targeted at media center applications. Toshiba selects ViXS' XCODE chip to provide video over IP networks by EDP Weekly's IT Monitor To keep their information fresh, ASFSA used an IBM computer with Reduced Instruction Set Computer (RISC) architecture. Satisfying members' appetites for information by Association Management	redraw Redressement Redruth redruthite Redshank redshift redstart Redstarts redstone Redstone Arsenal Redstone, Sumner redtop redtop grass reduce reduced characteristic equation reduced Compton wavelength reduced crude reduced cubic equation reduced distance reduced echelon matrix reduced equation Reduced Equation of State reduced form reduced frequency reduced inspection reduced instruction set computer reduced latitude reduced level Reduced Mass reduced nickel reduced oil Reduced Photometric Quantities reduced pressure reduced proper motion reduced property Reduced Residue System reduced residue system modulo n reduced size vent reduced telemetry reduced temperature reduced value reduced viscosity reduced volume Reduced Vowels Reduced Vowels, Loss Of reduced-order controller reduced-pressure distillation reduced-pressure-principle backflow preventer Reducer reducible configuration reducible curve	reduced glutathione reduced glutathione reduced glutathione Reduced Gradient Algorithm Reduced Gradient Bubble Model Reduced Gravity Student Flight Opportunities Program Reduced Gravity Student Flight Opportunity Reduced Gravity Student Flight Program Reduced Gravity Student Program Reduced Hazard Training Reduced Hazards Ammunition Reduced Height reduced hematin reduced hemoglobin reduced hemoglobin reduced hemoglobin Reduced Horizontal Separation Minima Reduced Human Performance Model Reduced Ignition Propensity Cigarette Reduced Impact Logging reduced in means Reduced in rank Reduced Income Tax Credit Reduced Injury Factor reduced inspection Reduced Instruction Set Architecture Reduced Instruction Set Class Reduced Instruction Set Code Reduced Instruction Set Code Reduced Instruction Set Code reduced instruction set computer Reduced Instruction Set Computer Operating System reduced instruction set computing reduced instruction set computing reduced instruction set computing reduced instruction set computing Reduced Instruction Set Model Reduced Instruction Set Quantum Reduced Intensity Conditioning Transplantation Reduced Intensity Transplant Reduced Interframe Spacing Reduced Interprocessor Communication Architecture Reduced iron Reduced Julian Day Reduced Laffrey Health Conception Scale Reduced Latency DRAM reduced latitude Reduced Length, Standard Diameter Miniature Passive Sonobuoy Reduced Level Reduced Level Reduced Level reduced lighting Reduced mass Reduced Material Condition Reduced Maternal Uterine Blood Flow Reduced Matrix Equation Reduced Media-Independent Interface Reduced Memory System Simulator Reduced Modified Nodal Analysis Reduced Mucobraomic Acid

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TAEC) has unveiled a new 32-bit single-chip MIPS-based reduced instruction set computer (RISC) microcontroller (MCU) family.

TOSHIBA UNVEILS 32-BIT SINGLE-CHIP MIPS BASED RISC MCU by Electro Manufacturing

The TX7901 MIPS reduced instruction set computer (RISC) processor-based AVM79R reference design is a leading-edge evaluation system targeted at media center applications.

Toshiba selects ViXS' XCODE chip to provide video over IP networks by EDP Weekly's IT Monitor

To keep their information fresh, ASFSA used an IBM computer with Reduced Instruction Set Computer (RISC) architecture.

Satisfying members' appetites for information by Association Management