SRAM


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SRAM

[′es‚ram]
(computer science)

SRAM

References in periodicals archive ?
The FM20L08 is a true surface-mount solution with no rework steps required for battery attachment and is highly resistant to negative voltage and undershoots that plague battery-backed SRAM.
The FM20L08 is organized as a 128K x 8 nonvolatile memory that reads and writes like a standard SRAM.
Quad data rate (QDR) and Double Data rate (DDR) families of SRAM with concurrent read/write capability can meet this challenge for high density memory that is capable of high speeds.
Availability of SRAM functionalities in embedded form is the major reason for the decline in the standalone SRAM market.
3V and 5V asynchronous SRAMS used with mainstream digital signal processors (DSPs) and microcontrollers.
By incorporating the Flash and SRAM in one package, AMD's MCP solutions can streamline procurement and inventory management as well as reduce overall system costs.
The device is also available in a multi-chip package (MCP), which includes the Am29BDS640G and an 8- or 16-Mb SRAM in a single, convenient package.
NYSE:MC) today announced the development of a technique that achieves stable operation with 45nm (nanometer) process generation bulk CMOS for SRAM (Static Random Access Memory) that can be embedded in SoC (system-on-a-chip) devices and microprocessors (MPUs).
In addition, Innovative Silicon has shown that this technology is less susceptible to soft errors than SRAM and comparable with embedded-DRAM.
Stable operation was verified by a 65nm test chip containing an 8Mbit, 6-transistor type SRAM with the world's smallest level memory cell area: 0.
A block of SRAM consists of 256 rows and 1024 columns, for a total of 256k bits per block.