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scan design
(redirected from Scan chain)

    Also found in: Wikipedia 0.03 sec.
(electronics)scan design - (Or "Scan-In, Scan-Out") A electronic circuit design technique which aims to increase the controllability and observability of a digital logic circuit by incorporating special "scan registers" into the circuit so that they form a scan path.

Some of the more common types of scan design include the multiplexed register designs and level-sensitive scan design (LSSD) used extensively by IBM. Boundary scan can be used alone or in combination with either of the above techniques.

["Digital Systems Testing and Testable Design" by Abramovici, Breuer, and Friedman, ISBN 0-7167-8179-4].

["Design of Testable Logic Circuits" by R.G. Bennetts, (Brunel/Southhampton Universities), ISBN 0-201-14403-4].


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With XJTAG, we can gain access to the boundary scan chain and get an interactive graphical view of all the device pins, and we can read or write pins and busses with a single click to test that they are free from opens and shorts.
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It also includes an input chain-mask controller and an input-mask network for driving constant logic values into scan chain inputs of selected scan chains to allow designers to recover from scan chain hold time violations.
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