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scan design
(redirected from Scan chain)

   Also found in: Wikipedia 0.01 sec.
(electronics)scan design - (Or "Scan-In, Scan-Out") A electronic circuit design technique which aims to increase the controllability and observability of a digital logic circuit by incorporating special "scan registers" into the circuit so that they form a scan path.

Some of the more common types of scan design include the multiplexed register designs and level-sensitive scan design (LSSD) used extensively by IBM. Boundary scan can be used alone or in combination with either of the above techniques.

["Digital Systems Testing and Testable Design" by Abramovici, Breuer, and Friedman, ISBN 0-7167-8179-4].

["Design of Testable Logic Circuits" by R.G. Bennetts, (Brunel/Southhampton Universities), ISBN 0-201-14403-4].


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So if your design uses Boundary Scan parts, ensure that the scan chain has been implemented correctly (FIGURE 3).
00 Paperback TK7874 The 54 papers selected for the April 2008 symposium are divided into sessions on testing for high-speed communication systems, compaction, ATE data volume, diagnosis of scan chains, memory diagnosis and repair, nanometer CMOS, analog circuits, ATPG, RF circuits, testing of transition faults, and mixed signal circuits.
Data can be shifted into and out of the scan chain connecting the boundary scan cells on multiple devices on a board.
 
 
 
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