shift register

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shift register

[′shift ‚rej·ə·stər]
(computer science)
A computer hardware element constructed to perform shifting of its contained data.

shift register

A high-speed circuit that holds some number of bits for the purpose of shifting them left or right. It is used internally within the processor for multiplication and division, serial/parallel conversion and various timing considerations.
References in periodicals archive ?
IN is connected to each DFF's reset (RES) port, effectively setting all register values to 0, except for the last DFF in the shift register.
The string of bits corresponding to the coefficients of the generated polynomials is used for the construction of a shift register linear feedback.
Many of the parts used to make the current shift registers are obsolete or becoming obsolete.
All memory blocks include extra parity bits for error control, embedded shift register functionality, mixed width mode, and mixed clock mode support.
The three new devices each contain 24 Twin Generic Logic Blocks (Twin GLBs(TM)) that provide 192 macrocells of general-purpose programmable logic, along with a 4K bit optimized Memory Module and a programmable Register/Counter Module optimized for read/write register, shift register, counter and timer functions.
The PSD835G2 has a 3,000 gate CPLD that designers can use to design custom peripherals, such as loadable shift registers and counters, state machines, and mail boxes.
With 82 inputs and 24 outputs, the CPLD provides enough on-chip programmable logic to implement peripheral functions, such as shift registers, mail boxes, and serial channels.
The Xilinx Spartan and Virtex devices offer powerful features such as high-performance shift registers, BlockRAM(TM), Distributed RAM, and delay-locked loop (DLL) circuits that operate at clock speeds up to 200 MHz," said Robert Bielby, director of strategic applications at Xilinx.
In order to meet customer demands for off-the-shelf high speed video shift registers, Vitesse Semiconductor Corp.
It easily interfaces with standard shift registers or microprocessors.
The 3,000 gate CPLD on the PSD813F devices is sufficient to implement dual processor interfaces, mail boxes, keypad scanners, timers, counters, interrupt controllers, shift registers and other functions.
This is sufficient programmable logic to implement complex peripheral functions including dual processor interfaces, mail boxes, keypad scanners, timers, counters, interrupt controllers, shift registers and others.