Supplemental SSE3 definition of Supplemental SSE3 in the Free Online Encyclopedia.

SSE

(1) An earlier full-screen editor in OS/2.

(2) (Streaming SIMD Extensions) A series of additional instructions built into Pentium CPU chips for improved multimedia performance by performing mathematical operations on multiple sets of data at the same time (see SIMD). The first SSE set was 70 new instructions built into the Pentium III, which also added eight 128-bit integer registers to the CPU.

Integers and Floating Point
The extra registers enable multiple sets of integer and floating point data to be calculated at the same time. SSE works with all standard data types, including single and double precision floating point and any integer from eight to 128 bits.

Prior to SSE, the first multimedia instructions for Pentium chips were the MMX additions. MMX used a part of the floating point registers for integer calculations, and floating point and MMX operations were mutually exclusive (see MMX).

SSE2 and SSE3
The Pentium 4 added 144 more instructions (SSE2) that were also incorporated by AMD in its 64-bit CPUs. However, AMD added eight more registers than Intel for use in 64-bit mode. Intel subsequently included the extra eight registers for its Intel 64 (EM64T) 64-bit processors.

Coinciding with Intel's Prescott CPUs, 13 more instructions were added (SSE3) in 2004 for 32-bit Pentiums, especially suited for MPEG encoding. See MMX, Prescott, SIMD and Pentium.

Supplemental SSE3
The Core 2 architecture includes 16 additional instructions that work on four 32-bit chunks of data at the same time to accelerate the processing of computation-intensive algorithms such as for compressing and decompressing video. See Core 2.

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SSE (redirected from Supplemental SSE3)

SSE
(redirected from Supplemental SSE3)