Viterbi decoder


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Viterbi decoder

A decoding algorithm developed in the late 1960s by Andrew Viterbi that is used to decode a particular convolutional code. Viterbi decoders have been the most effective way to decode wireless voice communications in satellite and cellphone transmissions. Viterbi outputs a 0 or a 1 based on its estimate of the input bit. See CDMA, convolutional code and turbo code.


Using the Viterbi Decoder
In the CDMA technology, the Viterbi decoder in the cellphone is used to correct the errors in the convolutional code that was generated by the base station. See CDMA.
References in periodicals archive ?
Give the received data to the Viterbi decoder for decoding.
6 release provides a total of four new AccelWare cores and an additional ten cores with new micro-architectures, including a Viterbi decoder, a Reed-Solomon decoder, polyphase decimation filters with programmable coefficients, and various micro-architectures, including radix-4 FFT/IFFT and FIR filters.
DSP functions used in communications subsystems such a FEC 32-channel Viterbi decoder core** can now be implemented in a Spartan-3 FPGA (XC3S1000) for an effective price of $0.
Additional IP modules that Lattice intends to make available for its ECP and EC devices include DDR Memory Controller, FCRAM Memory Controller, Viterbi Decoder, Turbo Decoder, and Numerically Controlled Oscillator.
Consisting of a convolutional encoder and Viterbi decoder, the Viterbi IP core supports error correction for both burst mode and continuous data input.
The additions to the AccelWare IP include parameterized models for a Viterbi decoder, Galois field operators, polyphase decimation filters with programmable coefficients, radix-4 FFTs and IFFTs, and FIR filter serial-distributed arithmetic (SDA) and parallel-distributed arithmetic (PDA) architectures.
Additionally, the release includes significant enhancements to several existing IP cores, including the general purpose Viterbi Decoder the Multiply-Accumulate-based Finite Impulse Response (MAC FIR) Filter, the Direct Digital Synthesizer (DDS), and the CORDIC.
Design aspects of the STE1000P patented by ST include improvements in the implementation of the PMD Viterbi decoder, the timing recovery circuit, the analog feedforward and adaptive digital gain controls and the low-power adaptive finite impulse response digital filter.
In addition, customers can obtain AltiVec technology-related application notes with software code that solve specific real-life problems in such application areas as TCP/IP, Complex FIR, GSM Soft-Decision Viterbi Decoder and GSM Convolution Encoder.
The functions provided include bit synchronizer, code converter, Viterbi decoder, frame synchronizer, Bit Error Rate Tester (BERT) and PCM simulator.
According to this plan, GDA will release a highly configurable and high performance 10GB MAC, Utopia Level3 Interface, Viterbi decoder and FFT intellectual property blocks in Q2, 2001.
The new algorithms include an enhanced Reed-Solomon Encoder/ Decoder, a Convolutional Encoder, a Viterbi Decoder, a Turbo Convolutional Code Encoder/Decoder, and an Interleaver/De-interleaver.