LVDS

(Low Voltage Differential Signaling) A balanced digital transmission method that is noted for its high-quality signal (low noise). LVDS is used in myriad applications, including LCD monitors, network and peripheral devices, A/V equipment and automotive systems. An option for the SCSI interface, LVDS doubled the cable length from six to 12 meters (see SCSI signaling). See noise.

Differential vs. Data and Ground
LVDS sends data over "data high" and "data low" lines rather than data and ground. The receiver detects the voltage difference between the two signals instead of relative to ground. See differential signaling, TMDS, OpenLDI and automotive Ethernet.

Flat Panel Monitor

This diagram of a typical flat panel monitor shows how LVDS is used as the last interface to the display panel itself. (Redrawn from original courtesy of Analog Devices, Inc.)

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References in periodicals archive

Its PCI Gen.3 interface allows access to control and status registers for controlling algorithms, state machines and data flow across the LVDS I/O front panel and carrier board interfaces.

Pentek's Jade Architecture Digital I/O XMC Module Now Available

LVDS I/O, high-speed isolator and LDO for flexible 2.5/3.3V supply combined in a single SOIC-W package

ANALOG DEVICES UNVEILS LVDS DIGITAL ISOLATOR SERIES

Hitachi DPG said that integrating the LVDS data interface onto a TFT display module allows high speed digital transmission of the image data with low power consumption, excellent tolerance to transmission line effects and exceptional noise immunity which ensures a clear, crisp display image at all times.

Hitachi DPG offers LVDS TFT displays to support SBC applications

The LVDS screened flat cables are a real alternative to twisted pairs and miniature coaxials for a lower cost and better performance.

AxolinkA : Flat Display Connections

FPGA architectures have evolved to support LVDS pairs.

An integrated approach to designing-in FPGAS: FPGA/PCB integration is time consuming and error-prone. Automating communication between the flows can eliminate the impact of an FPGA I/O design change on the PCB design

The ease-to-use features are, among others, control hardware and software that converts PC LPT port to the DS92UT16's microprocessor port timing, and two on-board clock oscillators, 33 MHz for the Utopia clocks and 52 MHz for the LVDS clocks.

NAT'L SEMICONDUCTOR DEBUTS UTOPIA-LVDS REFERENCE DESIGN KIT

The physical signaling is standard LVDS operating from 100MHz to 1GHz.

RaoidIO Zooms Through The Box!

The GPIO-1 provides a high-performance 66 MHz PCI interface with up to 256 MB of on-board, SDRAM memory and 64 bits of bi-directional I/O signals, with each signal presenting the option of driving or receiving TTL, CMOS, LVTTL, LVDS, GTL or HSTL levels.

PMC module

The part uses CML logic levels for all I/Os and is comapatible with legacy PECL and LVDS interfaces.

Common Mode Logic IC

The Model 71813 is based on the Xilinx Kintex Ultrascale FPGA and features 28 pairs of LVDS digital I/O to meet the requirements of emerging standards from The Open Group Sensor Open Systems Architecture[TM] (SOSA[TM]) Consortium of which Pentek is a member.

Pentek's Jade Architecture SOSA Aligned LVDS XMC Module with Optical I/O Now Available

has launched an industry-first motor driver product, THM3561, with input/output of LVDS or Low Voltage Differential Signaling.

THINE LAUNCHES MOTOR DRIVER WITH LVDS INPUT/OUTPUT