MIPS R2000

(processor)

The R2000 design came, in about 1987, from the Stanford MIPS project, which stood for Microprocessor without Interlocked Pipeline Stages.

Like the AMD 29000, the R2000 has no condition code register considering it a potential bottleneck. The program counter can be read like other registers.

The CPU includes an MMU that can also control a cache, and the CPU can operate as big-endian or little-endian. There is a FPU, the R2010.

Versions include the MIPS R3000 and MIPS R4000.

This article is provided by FOLDOC - Free Online Dictionary of Computing (foldoc.org)

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References in periodicals archive

Our goal was to translate most user mode MIPS programs compiled for a MIPS R2000 or R3000 machine running ULTRIX Release 4.0 (or later) to run identically on the DEC OSF/1 AXP system with acceptable performance.

Binary translation

Mountain View, Calif.) reduced to 10,000 the price of its Personal Iris 4D/2D, which is built around the Mips R2000 RISC processor.

Workstation prices plummet

The progress that has been made during the last three or four years is well illustrated by comparing the MIPS R2000 processor developed in 1986 with two-micron technology, with the Intel i860 developed in 1989.

The rise of the VLSI processor

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