Conditional branch scripting is very easy to set up to take care of customer objections.
In both the architecture and compiler domains,
conditional branch instructions are a barrier to higher levels of performance.
To reduce the overhead on a cache miss, we propose a cache miss trap that is more like a
conditional branch than a conventional trap.
The branch unit can only resolve a single CR bit at a time, thus it can only speculate down one
conditional branch path at a time.
The example in Figure 2 shows how a loop with a
conditional branch can be software pipelined with a variable initiation interval.
It was noticed that the sc has a high percentage of
conditional branch and high cache-miss ratios compared to other integer applications.
Our implementation of the heuristics took these factors into account, constructing an abstract syntax tree from the program binary and using that to determine the outcome of the
conditional branch. Clearly, determining this information at compile time would simplify the analysis, since more program information would be available.