A negative gate potential [V.sub.GS] is applied to the bottom side of the p-type silicon substrate such that a negatively charged
depletion layer appears under the buried oxide layer.
Similarly the boundary conditions for time varying normalized current density (P(x,t) = ([J.sub.p](x,t) - [J.sub.n](x,t))/[J.sub.t](t)) at the
depletion layer edges (i.e., at x = 0 and x = W) are given by
If the thickness of Sn[O.sub.2] sample decreases, the ratio of the thickness of
depletion layer and thickness of the sample increases; the sample of Sn[O.sub.2] thin layer can be depleted as a whole and the conductance of the sample is small [22, 29].
The higher result obtained for n-Sn[O.sub.2]/Si[O.sub.2]/n-Si device related to the increase in the
depletion layer width by adding the interfacial oxide thickness (Si[O.sub.2]) which means large area for electron-hole pairs separation and hence large photo-current.
First, it is clear that for high reverse gate-channel bias, the
depletion layer extends over most of the channel.
Here the zero bias
depletion layer formed under the metal acts as the topmost lossless layer.
Engineers who never had been quite certain of how the incident wave propagates across the MESFET gate strip, or the direction electrons flow in the presence of an electron
depletion layer will find the diagrams depicting the physical functioning of solid-state circuit elements, most enlightening.