linear-sweep delay circuit
linear-sweep delay circuit
[′lin·ē·ər ¦swēp di‚lā ‚sər·kət] (electronics)
A widely used form of linear time-delay circuit in which the input signal initiates action by a linear sawtooth generator, such as the bootstrap or Miller integrator, whose output is then compared with a calibrated direct-current reference voltage level.
McGraw-Hill Dictionary of Scientific & Technical Terms, 6E, Copyright © 2003 by The McGraw-Hill Companies, Inc.
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