structured ASIC

A type of application specific IC (ASIC) chip that contains blocks of logic, called "tiles" or "modules," that have their transistors already wired together forming gates along with some combination of multiplexors, flip/flops, look up tables and the like. Some vendors also include blocks of RAM. Unlike a standard cell, which requires all the masking stages in the transistors and metallization layers to be fabricated, structured ASICs require only one or two masks to tie the tiles together. In one design, only the vias need to be made conductive in order to complete the chip. See ASIC and via.

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References in periodicals archive

eASIC is a fabless semiconductor company offering breakthrough Structured ASIC devices aimed at dramatically reducing the overall fabrication cost and time of customized semiconductor chips.

CAST'S H.264-MCE ENCODER DELIVERS 150HZ PERFORMANCE

Altera's Quartus II design software is a technologically advanced development software for FPGA, CPLD, and structured ASIC designs.

SYNPLIFY PRO 7.5 SOFTWARE IMPROVES ALTERA'S STRATIX II DEVICES

(Nasdaq:LAVA), a provider of semiconductor design software, has announced that STMicroelectronics (NYSE:STM) has successfully implemented a via-programmable embedded structured ASIC platform using Magma's Blast Create(TM) SA.

ST IMPLEMENTS ASIC PLATFORM USING MAGNA'S BLAST CREATE

The expanded EasyPath product line now supports the Xilinx Spartan-3 and Virtex-4 Platform FPGAs, starting at just $12.95 for 30,000 logic cells and half the price of comparable Structured ASIC offerings.

Xilinx intros next-gen EasyPath FPGAs priced below structured ASICs

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