RISC-V

RISC-V

(Reduced Instruction Set Computer-5) An open source RISC-based instruction set developed at the University of California, Berkeley. RISC-V is the fifth project of its type, hence the V (5) in the name. RISC-V is a 32-bit CPU with 31 general-purpose registers; however, it can also be extended to 64 bits.

Designed for efficient processing in embedded systems, RISC-V is an extremely streamlined architecture with eight system calls and 39 essential instructions. The base instruction set excludes multiplication and division.

RISC-V Extensions
Depending on the intended application, the RISC-V architecture can be augmented with numerous extensions such as support for 64 and 128 bit virtual memory paging, compressed instructions to save memory, multiplication and division, floating point math, bit manipulation and interrupt handling. See RISC.

Copyright © 1981-2025 by The Computer Language Company Inc. All Rights reserved. THIS DEFINITION IS FOR PERSONAL USE ONLY. All other reproduction is strictly prohibited without permission from the publisher.