address bus


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address bus

[′ad·res ‚bəs]
(computer science)
An internal computer communications channel that carries addresses from the central processing unit to components under the unit's control.

address bus

(processor)
The connections between the CPU and memory which carry the address from/to which the CPU wishes to read or write. The number of bits of address bus determines the maximum size of memory which the processor can access.

See also data bus.

address bus

An internal channel from the CPU to memory across which the addresses of data (not the data) are transmitted. The number of lines (wires) in the address bus determines the amount of memory that can be directly addressed as each line carries one bit of the address. For example, a 20-line address bus represents the binary number 1,048,576 and reaches that number of memory bytes (the size of the address bus in the IBM PC in 1981). A computer with a 32-bit address bus can directly address 4GB of physical memory, while one with 36 bits can address 64GB.


References in periodicals archive ?
Addresses to cache RAM are derived from ADR (16-2) lines of address bus.
Using microcontrollers with large address bus and higher resolution.
Access to the data and address bus of the industry leading ARM7TDMI(TM) CPU -- Enables the addition of DSP processors, USB host devices, additional SRAM, etc.
The ARM610 RISC microprocessor features a 32-bit data bus and a 32-bit address bus, an on-chip memory management unit, a 4K-byte mixed cache and a write buffer.
Defined with minimal overhead, the Atlantic interface utilizes approximately 10 control signals in addition to a variable width data bus, and an optional address bus.
The MCA bus model also features a new 32-bit MicroChannel address bus interface that improves performance in servers with more than 16 MBytes of main memory.
Defined with minimal overhead, Atlantic utilizes approximately 10 control signals in addition to a variable width data bus, and an optional address bus.
For example, the 68EC020's 24-bit address bus, as opposed to the 68020's 32-bit bus, enables reduced chip-size and therefore lower costs.
MIPS instruction set -- 36-bit address bus (64-bit virtual address), 64-bit data bus -- 8KB instruction cache, 8KB data cache with 8-bit error detection & correction -- 25MHz pipeline frequency -- 50MHz external clock (a selectable feature for the bus clock rate) -- 64-bit general-purpose registers, integer unit, floating point registers, and floating point unit -- Operating voltage of 3.
The CSI bus consists of a 32-bit address bus and a 32-bit data bus, running at transfer rate of up to 265Mbytes per second.
3DSP's new bus controller can support up to 15 simultaneous data transfers with zero overhead arbitration and has a single data bus and an address bus shared among peripherals.