address decoder


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address decoder

A circuit that converts an address into the electrical signals required to retrieve the data from a memory cell, disk sector, cartridge library or other memory or storage device.
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Toshiba slightly modified the address decoder inside the NAND EEPROM to enable the lines between two devices to be connected.
An SOC Kernel includes the IP cores common to most 32-bit systems: interrupt controller, timers, interface for parallel inputs and outputs, address decoder, an internal memory controller (with a memory model), system bus interface elements, and a microprocessor interface.
3v, this device offers two NS16C550 high speed UARTS (Universal Asynchronous Receiver Transmitter) with send/receive 16 Byte FIFOs, ISA host interface, general purpose address decoder, multi-mode parallel port with ChiProtect(TM) and EPP/ECP support.
The ZPSD6XX also has a built-in address decoder and MCU interface.
The TSC, or the "core" of the chip set and the TDP, the path to memory, comprise a host-PCI bridge that provides functions such as a 64-bit host bus interface, a 32-bit PCI interface, a 64-bit main memory interface, a write-back second-level cache interface, a host and PCI address decoder, and a PCI bus arbiter.
encoders/decoders, address decoders, cache controllers, and arbitration
The pLSI and ispLSI 2000 family of high density PLDs, boasting the industry's fastest performance, will target high-performance, speed- critical applications such as address decoders, small state machines, processor bus interfaces, counter/timers and glue logic.
The A32140DX device features fast, wide decode modules permitting easy implementation of high-speed state machines and address decoders typically implemented in CPLDs.