branch prediction


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branch prediction

[′branch prə‚dik·shən]
(computer science)
A method whereby a processor guesses the outcome of a branch instruction so that it can prepare in advance to carry out the instructions that follow the predicted outcome.

branch prediction

(processor, algorithm)
A technique used in some processors with instruction prefetch to guess whether a conditional branch will be taken or not and prefetch code from the appropriate location.

When a branch instruction is executed, its address and that of the next instruction executed (the chosen destination of the branch) are stored in the Branch Target Buffer. This information is used to predict which way the instruction will branch the next time it is executed so that instruction prefetch can continue. When the prediction is correct (and it is over 90% of the time), executing a branch does not cause a pipeline break.

Some later CPUs simply prefetch both paths instead of trying to predict which way the branch will go.

An extension of the idea of branch prediction is speculative execution.

branch prediction

In CPU instruction execution, predicting the outcome of a branch so that those instructions may be executed in parallel with the current instructions. If the CPU guesses the wrong branch, it will take extra machine cycles to go back and execute the correct one; however, on average, if the prediction algorithms are good, overall performance is increased. See predication and branch.
References in periodicals archive ?
where N is the number of index bits used for the branch prediction table.
The first proposal of this Thesis is the Branch Prediction Reversal Unit (BPRU), a mechanism that selectively reverses those branch predictions likely to be mispredicted in order to improve branch prediction accuracy.
Branch prediction is a common technique used to overcome this performance limitation imposed on high performance architectures and is the key to many techniques for enhancing ILP.
Tag comparison, branch prediction, and instruction decode are outside the critical fetch loop [5].
74K Core Feature Highlights: -- High Performance Floating Point Unit -- Two pipelines support asymmetric dual-issue -- Advanced Branch Prediction -- Three 256-entry Branch History Tables -- 8-entry Return Prediction Stack -- Extensive Clock Gating for low power: Fine Grain, Block Level, Top Level -- Support for L2 Cache -- including the MIPS SOC-it(R) L2 Cache Controller The MIPS32 74K Core Family
In these proceedings from the July 2005 conference, contributors describe their work in energy-aware computing (including speed modulation), worst-case execution time analysis (including a WCET- oriented branch prediction system), programming languages, modeling and validation techniques including model-based and component-based approaches, operating system support, scheduling and "schedulability" analysis, quality-of-service support and wireless sensor networks (including scheduling task with Markov-chain-based constraints), multiprocessor systems, and applications of real-time computing.
The ARM1136J-S processor's improved branch prediction and additional execution units provide increased efficiency, resulting in overall superior performance.
The VIA Eden-N processor comes packed with advanced performance features such as StepAhead(TM) Advanced Branch Prediction, sixteen pipeline stages, support for SSE multimedia instructions, a full-speed Floating Point Unit (FPU) and an efficiency-enhanced 64KB Full-Speed Exclusive L2 cache with 16-way associativity for memory optimization.
Key features include: Micro-Ops Fusion, which combines two micro-operations into one, enabling it to execute faster and at lower power; Advanced Branch Prediction -- a new implementation technique -- to help to reduce overall latency in the system contributing to higher performance at lower power; and the Dedicated Stack Manager, which reduces the overall number of micro-operations required to generate higher performance at lower power.
For added system performance, the PowerPC 440 includes dynamic branch prediction, 24 DSP instructions, and non-blocking caches that can be managed in either a write-through or write-back mode.
Implemented using Texas Instruments' 90 nanometer process technology, UltraSPARC IV+ will double the application throughput of the existing UltraSPARC IV through expanded caches and buffers, a better branch prediction mechanism, augmented prefetching capabilities and new computational abilities.
Some of the Banias architectural enhancements include branch prediction, instruction combination, and bus power optimization.