buffered FET logic

buffered FET logic

[′bəf·ərd ¦ef¦ē¦tē ′läj·ik]
(electronics)
A logic gate configuration used with gallium-arsenide field-effect transistors operating in the depletion mode, in which the level shifting required to make the input and output voltage levels compatible is achieved with Schottky barrier diodes. Abbreviated BFL.