bus architecture


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bus architecture

[′bəs ′är·kə‚tek·chər]
(computer science)
A structure for handling data transmission in a computer system or network, in which components are all linked to a common bus.

bus architecture

A shared input/output pathway, typically between the CPU and peripheral devices. See bus.
References in periodicals archive ?
As the demands on PCI have increased, the limitations inherent in bus architecture are creating an overall system bottleneck.
Additionally, the plug and play nature of the PCI bus architecture eliminates installation and configuration issues, making it very easy to install.
PCI Express expansion bus architecture is now used with increasing frequency by leading server manufacturers.
In contrast, Ultra320 SCSI's shared bus architecture is restricted to 320 MB/sec for all attached devices.
According to IBM, an industry-standard bus architecture would enable chip manufacturers to mix and match a range of IP modules or cores developed by chip designers, speeding SOC development time and boosting functionality.
The PCI local bus architecture brings peripheral functions closer to the microprocessor and improves system performance up to eight times more than older bus designs such as EISA, ISA or MCA.
Development of the ATA/ATAPI-7 specification, an update of the parallel bus architecture that provides up to 133MB/sec, is currently being finalized (see www.
Wyse's Wyde Bus architecture is compatible with major open operating systems and their broad applications base.
The Sensei Series converters are designed for Intermediate Bus Architecture (IBA) and Distributed Power Architecture (DPA) applications that require high efficiency and high reliability in elevated temperature environments.
Under this agreement, Weitek's user interface controllers will be tightly coupled with VLSI's local bus architecture, producing dramatic performance improvements for users of Microsoft's Windows and its applications.
It was determined that no single vendor could meet their needs with a single solution, thus, the project was divided into two distinct components: 1) real-time application-independent data capture, and 2) an enterprise message bus architecture with a Complex Event Processing (CEP) engine for developing the fraud detection rules.
The bus architecture allows the scalable, modular approach to solving the complex problem of bringing together device control with video and audio signal routing.