bus error


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bus error

(processor)
A fatal failure in the execution of a machine language instruction resulting from the processor detecting an anomalous condition on its bus. Such conditions include invalid address alignment (accessing a multi-byte number at an odd address), accessing a physical address that does not correspond to any device, or some other device-specific hardware error. A bus error triggers a processor-level exception which Unix translates into a "SIGBUS" signal which, if not caught, will terminate the current process.
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Other features of the AS8223 include: very low asymmetric delay contribution; data transfer up to 10 Mbps; enhanced bus error detection with current sensing on FlexRay branches up to 8 m from connector pins, plus very low contribution to the FlexRay network asymmetric delay.
Dual I/O buses from each server are connected to each CLARiiON storage processor, permitting alternate I/O paths and providing automatic I/O re-routing upon SCSI bus error detection.
Raytheon verified that no bus errors were reported on the legacy 1553 equipment during the flight.
The bus is normally only reset on bus errors that should never occur on the SCSI bus.
Bus errors and random bus hangs will occur with passive terminations with large configurations or high speed.
An ISS that is only instruction-level or cycle-accurate does not model events that occur inside the processor and, therefore, can produce inaccurate simulations for certain events such as bus errors, interrupts, and other exceptions that disrupt the flow of instructions in the processor's pipeline.