cache line


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Related to cache line: cache memory

cache line

(storage)
(Or cache block) The smallest unit of memory than can be transferred between the main memory and the cache.

Rather than reading a single word or byte from main memory at a time, each cache entry is usually holds a certain number of words, known as a "cache line" or "cache block" and a whole line is read and cached at once. This takes advantage of the principle of locality of reference: if one location is read then nearby locations (particularly following locations) are likely to be read soon afterward. It can also take advantage of page-mode DRAM which allows faster access to consecutive locations.

cache line

The block of memory that is transferred to a memory cache. The cache line is generally fixed in size, typically ranging from 16 to 256 bytes. The effectiveness of the line size depends on the application, and cache circuits may be configurable to a different line size by the system designer. There are also numerous algorithms for dynamically adjusting line size in real time. See cache.
References in periodicals archive ?
The authors evaluate a hybrid scheme which combines the three techniques and propose using transmission lines only to access the central banks where the cache lines are concentrated due to block migration.
The number of forward and backward pointers is proportional to the number of cache lines in the machine, which is much smaller than the number of memory lines.
Included are configurable cache line size options of 4 or 8 words to tune performance with applications needs.
On average assuming a cache line has four words, and on average two words per write are in cache then bus utilization improves by more than two-fold.
2 compliant, 33MHz, 32 bit PCI burst transfer rates of up to133MB/s; Multimode I/O cells supporting both Ultra2 (LVD) and/or legacy single-ended devices; PC99 compliant without external logic; 512 byte DMA FIFOs for more efficient PCI bus utilization: Support for FLASH for easy BIOS upgrades; Cache line streaming for improved PCI bus utilization.