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clock cycle

   Also found in: Wikipedia 0.04 sec.

clock cycle

See clock tick.



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To support both high speed and robust data transfer, the devices utilize advanced Rambus-specific features such as Differential Rambus Signal Level (DRSL) interface, which minimizes the signal swing and noise, and Octal Data Rate (ODR) which transfers 8 bits per clock cycle to achieve 3.
Advanced Transfer Cache consists of a 256-bit (32 byte) interface that transfers data on each core clock cycle.
Octal Data Rate (ODR), a technology that transfers eight bits of data on each clock cycle, four times as many as today's state-of-the-art memory technologies that use DDR (Double Data Rate) clocking;
 
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