clock frequency

clock frequency

[′kläk ‚frē·kwən·sē]
(electronics)
The master frequency of the periodic pulses that schedule the operation of a digital computer. Also known as clock rate; clock speed.

clock frequency

References in periodicals archive ?
A reliable clock frequency supply is essential to guarantee the quality of service required.
Features of the LS7082N, LS7083, LS7084, LS7183, and LS7184 include: x1, x2 or x4 frequency multiplication of the quadrature clock, programmable output clock pulse width, up to 16 MHz output clock frequency, and 3 V to 12 V operation.
Operating at the maximum clock frequency of the PowerPC 405 core, the new design loads and executes code exclusively from the integrated PowerPC 16KB instruction and 16KB data cache memory.
Over a similar timeframe, advances in silicon technology, driven by Moore's Law, have allowed the CPU clock frequency in the average PC to increase from roughly 25MHz to 2.
NEC Corp has developed a clock generation circuit which the company claims can increase the clock frequency of a central processing unit by two, four or even eight times while reducing power consumption by as much as a third.
During rest periods, HyperGear scales down the clock frequency for improved efficiency.
5GHz in turbo mode, this processor, which is worth $999 operates at a base clock frequency of 3.
Bus operations at 33 MHz and 66 MHz are supported, with the bridge automatically detecting the bus clock frequency.
The new memory cards support wider bus widths (x1, x4, x8) and a clock frequency of 52megahertz (MHz) to enable faster data transition rates.
New Release of Rubix[TM] Delivers 15% Increase in Clock Frequency and Full Support for CPF 1.
Additionally, Palmchip's patent-pending SpeedSelect technology allows the IDE core timings to be reprogrammed by software to support all ATA modes at virtually any clock frequency which is perfect for a wide range of applications from DVD drives up to the ultra fast 133Mhz UDMA storage drives.
The addition of this signal allows the system to control the effective clock frequency of the interface dynamically without introducing extra outputs from phase-locked loops, or requiring additional low-skew clock distribution networks when divided frequency clocks are used.