A similar pattern-related fault modelling approach, called functional fault model, was proposed earlier in  for the module-level fault diagnosis in combinational circuits based on solving systems of Boolean differential equations.
In this paper, we propose a hierarchical approach for the fault diagnosis in combinational circuits.
SOPRANO: An efficient automatic test pattern generator for stuck open faults in CMOS combinational circuits.
In this work is presented new multilevel multi-resource partitioning algorithm for partitioning large combinational circuits in order to efficiently use existing and commercially available FPGAs packages.
Combinational circuits could be very large and cluster partitioning helps obtaining more technological compliant mapping over the initial circuit.
Partitioning combinational circuits for k-LUT FPGA mapping.
We also developed fixed QCA circuit which can be used to get all Boolean logic functions and also to build combinational circuits such as comparators, parity generators and checkers.
We will discuss in the next session the use of QCA structure to form simple combinational circuits.
Aguirre, Towards Automated Evolutionary Design of Combinational Circuits, Comput.
A combinational circuit based on this minimal form offers the shortest response time, but not at all the smallest size.
In this paper is used simulation-based approach for 15 combinational circuits
of the MCNC benchmark.
After describing Simulink and Stateflow, he discusses Simulink model building for fault modeling and simulation for combinational circuits
and sequential circuits.